Deterministic communication across integrated wired and wireless networks is currently one of the big topics in research and standardization. 5G and TSN integration efforts are at the forefront of enabling the convergence of wired and wireless networks for Industry 4.0.In this paper, we investigate how synchronization and syntonization errors affect the achievable end-to-end time synchronization accuracy in integrated 5G and TSN networks. We specifically focus on the impact of the 5G System modeling a TSN transparent clock according to 3GPP Release 17.

The 5G Transparent Clock: Synchronization Errors in Integrated 5G-TSN Industrial Networks

As the signaling speeds continue to increase, maintaining Signal Integrity (SI) for the complete customer design space is a huge challenge. These constraints, along with the limitations of traditional methods of design space inclusion and channel behavior prediction pose significant risk to system design. Specific focus is needed on design space utilization techniques used for factoring in platform variability. Interfaces like PCIe Gen5/Gen6/Gen4 etc. exhibit higher order behaviors that can’t be modelled by current prediction algorithm like Response Surface Method (RSM). This leads to inaccurate system behavior understanding and results in unreliable platform design recommendations. To minimize design risk and achieve highly reliable scaling of Platform Design Guide (PDG) solution, this paper discusses the implementation of an Artificial Intelligence (AI) based methodology to cover complete design space and predict higher order system behaviors with high accuracy. Current SI method involves RSM type Design of Experiments (DOE) creation and results prediction using second order RSM as shown in Fig. 2(a). It has limitations since RSM uses only three variable levels therefore doesn’t cover the entire design space. It can only model up to second order system behavior. These issues can be addressed using proposed AI based methodology shown in Fig. 2(b). These AI techniques have been encapsulated into an AI based tool called Fitpro which fully automates space filled DOE creation and SI results prediction. Fitpro significantly reduces manual interventions and positively impacts efficiency.

Artificial Intelligence based advanced Signal Integrity prediction

As the signaling speeds continue to increase, maintaining Signal Integrity (SI) for the complete customer design space is a huge challenge. These constraints, along with the limitations of traditional methods of design space inclusion and channel behavior prediction pose significant risk to system design. Specific focus is needed on design space utilization techniques used for factoring in platform variability. Interfaces like PCIe Gen5/Gen6/Gen4 etc. exhibit higher order behaviors that can’t be modelled by current prediction algorithm like Response Surface Method (RSM). This leads to inaccurate system behavior understanding and results in unreliable platform design recommendations. To minimize design risk and achieve highly reliable scaling of Platform Design Guide (PDG) solution, this paper discusses the implementation of an Artificial Intelligence (AI) based methodology to cover complete design space and predict higher order system behaviors with high accuracy. Current SI method involves RSM type Design of Experiments (DOE) creation and results prediction using second order RSM as shown in Fig. 2(a). It has limitations since RSM uses only three variable levels therefore doesn’t cover the entire design space. It can only model up to second order system behavior. These issues can be addressed using proposed AI based methodology shown in Fig. 2(b). These AI techniques have been encapsulated into an AI based tool called Fitpro which fully automates space filled DOE creation and SI results prediction. Fitpro significantly reduces manual interventions and positively impacts efficiency. 

As the signaling speeds continue to increase, main-taining Signal Integrity (SI) for the complete customer design space is a huge challenge. These constraints, along with the limitations of traditional methods of design space inclusion and channel behavior prediction pose significant risk to system design. Specific focus is needed on design space utilization techniques used for factoring in platform variability. Interfaces like PCIe Gen5/Gen6/Gen4 etc. exhibit higher order behaviors that current prediction algorithm like Response Surface Method (RSM) simply cannot model. This leads to inaccurate system behavior understanding and results in unreliable platform design recommendations. To minimize design risk and achieve highly reliable scaling of Platform Design Guide (PDG) solution, this paper discusses the implementation of an Artificial Intelligence (AI) based methodology to cover complete design space and predict higher order system behaviors with high accuracy. The goal is to achieve a model with at least 90 % R square and maximum 5% of result range Root Mean Square Error (RMSE). Current SI method of Design of Experiments (DOE) creation and results prediction consists of creating a combined RSM type DOE table and fitting it with second order RSM modelling in JMP as shown in Fig.2(a). It has limitations since RSM uses only three variable levels therefore doesn’t cover the entire design space. It can only model up to second order system behavior. These issues can be addressed using proposed AI based methodology which effectively captures the complete design variance using space filling algorithm shown in Fig.2(b). Paired with this, various AI based algorithms are explored for advanced SI results prediction. These techniques have been encapsulated into an AI based tool which supports automatic DOE creation and predicts the system behavior post simulation in a SINGLE ITERATION. This helps reduce manual interventions and improve efficiency along with highly desirable R square and RMSE values. 

Compared with the traditional support vector machine regression (SVR), the SVR hyperparameter fast optimization algorithm can improve the accuracy of the prediction results. However, the data shows that when the training sample is too large, it will increase the complexity of model learning, resulting in too long modeling time. Therefore, we refer to the most effective support vector set search method in the variable selection and sparse support vector machine (VSߝSSVM) algorithm, and appropriately fit the “advantages” of these two algorithms to construct a fast optimization hyperparameter and sparse support vector machine (FOH-SSVM) algorithm. In this work, we use the algorithm to solve the problem of signal integrity. The experimental results show that the modeling time required by the FOH-SSVM algorithm is 1%, which greatly reduces the modeling time. At the same time, the prediction accuracy of the algorithm is increased by 8%, ensuring good prediction performance.

Signal Integrity Analysis Based on SVR Improved Algorithm

The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second (PPS) signals. The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication.

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An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform

As we enter the 5G (5th-Generation) era, the amount of information and data has become increasingly tremendous. Therefore, electronic circuits need to have higher chip density, faster operating speed and better signal quality of transmission. As the carrier of electronic components, the design difficulty of high-speed PCB (Printed Circuit Board) is also increasing. Equal-length wiring is an essential part of PCB design. But now, it can no longer meet the needs of designers. Accordingly, in view of the shortcomings of the traditional equal-length wiring, this article proposes two optimization ways: the ”spiral wiring” way and the ”double spiral wiring” way. Based on the theoretical analysis of the transmission lines, the two optimization ways take the three aspects of optimizing the layout and wiring space, suppressing crosstalk and reducing reflection as the main points to optimize the design. Eventually, this article performs simulation and verification of schematic diagram and PCB of the optimal design by using HyperLynx simulation software. The simulation results show that these two ways not only improve the flexibility of the transmission line layout, but also improve the signal integrity of the transmission lines. Of course, this also proves the feasibility and reliability of the two optimized designs. Keywords—high-speed PCB, signal integrity, equal-length wiring, HyperLynx

Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity

A clock synchronization algorithm combining Kalman filter and fuzzy adaptive PI (proportional-integral) is proposed in this paper. Because of the system clock synchronization error caused by the delay jitter of the protocol stack and the CPU interrupt processing delay in the distributed network system. This algorithm uses Kalman filter to obtain the estimated value of clock offset and compensates the offset by introducing an adaptive fuzzy PI controller. While effectively filtering noise, it also improves the response speed of the slave clock and realizes the master-slave high precision and fast synchronization of the clock.

Fuzzy Adaptive PI Clock Synchronization Algorithm Based on Kalman Filter

As we enter the 5G (5th-Generation) era, the amount of information and data has become increasingly tremendous. Therefore, electronic circuits need to have higher chip density, faster operating speed and better signal quality of transmission. As the carrier of electronic components, the design difficulty of high-speed PCB (Printed Circuit Board) is also increasing. Equal-length wiring is an essential part of PCB design. But now, it can no longer meet the needs of designers. Accordingly, in view of the shortcomings of the traditional equal-length wiring, this article proposes two optimization ways: the "spiral wiring" way and the "double spiral wiring" way. Based on the theoretical analysis of the transmission lines, the two optimization ways take the three aspects of optimizing the layout and wiring space, suppressing crosstalk and reducing reflection as the main points to optimize the design. Eventually, this article performs simulation and verification of schematic diagram and PCB of the optimal design by using HyperLynx simulation software. The simulation results show that these two ways not only improve the flexibility of the transmission line layout, but also improve the signal integrity of the transmission lines. Of course, this also proves the feasibility and reliability of the two optimized designs.

/pdf/two-optimization-ways-of-ddr3-transmission-line-equal-length-2bhy34ou9f.pdf

Xiaohan Wei

Papers

Signal Integrity Analysis Based on SVR Improved Algorithm

An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform

Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity

Fuzzy Adaptive PI Clock Synchronization Algorithm Based on Kalman Filter

Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity