A wafer map contains a graphical representation of the locations about defect pattern on the semiconductor wafer, which can provide useful information for quality engineers. Various defect patterns occur due to increasing wafer sizes and decreasing features sizes, which makes it very complex and unreliable process to identify them. In this paper, we propose a voting ensemble classifier with multi-types features to identify wafer map defect patterns in semiconductor manufacturing. Our research contents can be summarized as follows. First, three distinctive features such as density-, geometry-, and radon-based features were extracted from raw wafer images. Then, we applied four machine learning classifiers, namely logistic regression (LR), random forests (RFs), gradient boosting machine (GBM), and artificial neural network (ANN), and trained them using extracted features of original data set. Then their results were combined with a soft voting ensemble (SVE) technique which assigns higher weights to the classifiers with respect to their prediction accuracy. Consequently, we got performance measures with accuracy, precision, recall, ${F}$ -measure, and AUC score of 95.8616%, 96.9326%, 96.9326%, 96.7124%, and 99.9114%, respectively. These results show that the SVE classifier with proposed multi-types features outperformed regular machine learning-based classifiers for wafer maps defect detection.

A Voting Ensemble Classifier for Wafer Map Defect Patterns Identification in Semiconductor Manufacturing

Wafer maps contain information about defects and clustered defects that form failure patterns. Failure patterns exhibit the information related to defect generation mechanisms. The accurate classification of failure patterns in wafer maps can provide crucial information for engineers to recognize the causes of the fabrication problems. In this paper, we proposed a decision tree ensemble learning-based wafer map failure pattern recognition method based on radon transform-based features. Radon transform is applied on raw wafer map data to generate the new features which are exhibiting the geometric information of failure patterns in wafer map. Decision tree algorithm is applied to build decision tree ensemble and the final decision is made by aggregating the prediction results of decision trees. The effectiveness of the proposed method has been verified by using the real world wafer map data set (WM-811K).

Decision Tree Ensemble-Based Wafer Map Failure Pattern Recognition Based on Radon Transform-Based Features

Electronics industry is one of the fastest evolving, innovative, and most competitive industries. In order to meet the high consumption demands on electronics components, quality standards of the products must be well-maintained. Automatic optical inspection (AOI) is one of the non-destructive techniques used in quality inspection of various products. This technique is considered robust and can replace human inspectors who are subjected to dull and fatigue in performing inspection tasks. A fully automated optical inspection system consists of hardware and software setups. Hardware setup include image sensor and illumination settings and is responsible to acquire the digital image, while the software part implements an inspection algorithm to extract the features of the acquired images and classify them into defected and non-defected based on the user requirements. A sorting mechanism can be used to separate the defective products from the good ones. This article provides a comprehensive review of the various AOI systems used in electronics, micro-electronics, and opto-electronics industries. In this review the defects of the commonly inspected electronic components, such as semiconductor wafers, flat panel displays, printed circuit boards and light emitting diodes, are first explained. Hardware setups used in acquiring images are then discussed in terms of the camera and lighting source selection and configuration. The inspection algorithms used for detecting the defects in the electronic components are discussed in terms of the preprocessing, feature extraction and classification tools used for this purpose. Recent articles that used deep learning algorithms are also reviewed. The article concludes by highlighting the current trends and possible future research directions.

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A Review and Analysis of Automatic Optical Inspection and Quality Monitoring Methods in Electronics Industry

Defective die on a wafer map tend to cluster in distinguishable patterns, and such defect patterns can provide crucial information to identify equipment problems or process failures in the semiconductor manufacturing. Therefore, it is important to accurately and efficiently classify the defect patterns. In this paper, we propose a novel clustering-based defect pattern detection and classification framework for wafer bin map (WBM). The proposed framework has many advantages. Outlier detection and defect cluster pattern extraction can be done at the same time; arbitrarily shaped cluster patterns can be detected; and there is no need to specify the number of clusters in advance. Based on WBM property, the parameters used in the clustering algorithm are fixed so that parameter sensitivity can be avoided. Since the defect patterns are classified based on extracted features, no labeled data and no supervised classification training are needed and single-type patterns as well as mixed-type patterns can be found. Extensive experiments conducted on a real-world WM-811K dataset has shown the superiority of proposed framework. The proposed framework can also be used in a big data environment to accelerate performance.

A Novel DBSCAN-Based Defect Pattern Detection and Classification Framework for Wafer Bin Map

Stacked convolutional sparse denoising auto-encoder for identification of defect patterns in semiconductor wafer map

In semiconductor manufacturing processes, defect detection and recognition in wafer maps have received increasing attention from semiconductor industry. The various defect patterns in wafer maps provide crucial information for assisting engineers in recognizing the root causes of the fabrication problems and solving them eventually. This paper develops a manifold learning-based wafer map defect detection and recognition system. In this system, a joint local and nonlocal linear discriminant analysis (JLNDA) is proposed to discover intrinsic manifold information that provides the discriminant characteristics of the defect patterns. An unsupervised version of JLNDA (called local and nonlocal preserving projection) is further developed to provide a monitoring chart for defect detection of wafer maps. A JLNDA-based Fisher discriminant is further put forward for online defect recognition without the modeling procedure of recognizers. Comparisons with other regular methods, principal component analysis, local preserving projection, linear discriminant analysis (LDA) and local LDA, illustrate the superiority of JLNDA in wafer map defect recognition. The effectiveness of the proposed system has been verified by experimental results from a real-world data set of wafer maps (WM-811K).

Xiaolei Lu

Papers

Wafer Map Defect Detection and Recognition Using Joint Local and Nonlocal Linear Discriminant Analysis