IEEE Transactions on Semiconductor Manufacturing 

About: IEEE Transactions on Semiconductor Manufacturing is an academic journal published by IEEE Computer Society. The journal publishes majorly in the area(s): Wafer & Computer science. It has an ISSN identifier of 0894-6507. Over the lifetime, 1999 publications have been published receiving 45716 citations. The journal is also known as: Institute of Electrical and Electronics Engineers transactions on semiconductor manufacturing & Transactions on semiconductor manufacturing.

Scheduling semiconductor wafer fabrication

Abstract: The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer fabrication. Certain of these scheduling rules are derived by restricting attention to the sub-set of stations that are heavily utilized, and by using a Brownian network model, which approximates a multi-class queuing network model with dynamic control capability. Three versions of the wafer fabrication model, which differ only by the number of servers present at particular stations, are studied. The three versions have one, two, and four stations, respectively, that are heavily utilized (near 90% utilization). The simulation results indicate that scheduling has a significant impact on average throughput time, with larger improvements coming from discretionary imput control than from lot sequencing. The effects that specific sequencing rules have are highly dependent on both the type of input control used and the number of bottleneck stations in the fabrication. >

Material removal mechanism in chemical mechanical polishing: theory and modeling

Abstract: The abrasion mechanism in solid-solid contact mode of the chemical mechanical polishing (CMP) process is investigated in detail. Based on assumptions of plastic contact over wafer-abrasive and pad-abrasive interfaces, the normal distribution of abrasive size and an assumed periodic roughness of pad surface, a novel model is developed for material removal in CMP. The basic model is MRR=/spl rho//sub w/NVol/sub removed/, where /spl rho//sub w/ is the density of wafer N the number of active abrasives, and Vol/sub removed/ the volume of material removed by a single abrasive. The model proposed integrates process parameters including pressure and velocity and other important input parameters including the wafer hardness, pad hardness, pad roughness, abrasive size, and abrasive geometry into the same formulation to predict the material removal rate (MRR). An interface between the chemical effect and mechanical effect has been constructed through a fitting parameter H/sub w/ a "dynamical" hardness value of the wafer surface, in the model. It reflects the influences of chemicals on the mechanical material removal. The fluid effect in the current model is attributed to the number of active abrasives. It is found that the nonlinear down pressure dependence of material removal rate is related to a probability density function of the abrasive size and the elastic deformation of the pad. Compared with experimental results, the model accurately predicts MRR. With further verification of the model, a better understanding of the fundamental mechanism involved in material removal in the CMP process, particularly different roles played by the consumables and their interactions, can be obtained.

Fifty Years of Moore's Law

Abstract: The 1959 invention of the planar silicon transistor led to the development of the integrated circuit (IC) and the growth trend in IC complexity known as Moore's Law While Moore's observation came in 1965, his original trend line showing a doubling of components per chip each year began with one component in 1959 Thus, we have now experienced 50 years of Moore's Law This paper provides a history of Moore's Law through its many changes and reinterpretations, containing possibly a few new ones as well

Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing plants

Abstract: The problem of reducing the mean and variance of cycle time in semiconductor manufacturing plants is addressed. Such plants feature a characteristic reentrant process flow, where lots repeatedly return at different stages of their production to the same service stations for further processing, consequently creating much competition for machines. We introduce a new class of scheduling policies, called Fluctuation Smoothing policies. Unanimously, our policies achieved the best mean cycle time and Standard Deviation of Cycle Time, in all the configurations of plant models and release policies tested. As an example, under the recommended Workload Regulation Release policy, for a heavily loaded Research and Development Fabrication Line model, our Fluctuation Smoothing policies achieved a reduction of 22.4% in the Mean Queueing Time, and a reduction of 52.0% in the Standard Deviation of Cycle Time, over the baseline FIFO policy. These conclusions are based on extensive simulations conducted on two models of semiconductor manufacturing plants. The first is a model of a Research and Development Fabrication Line. The second is an aggregate model intended to approximate a full scale production line. Statistical tests are used to corroborate our conclusions. >

Fault Detection Using the k-Nearest Neighbor Rule for Semiconductor Manufacturing Processes

Abstract: It has been recognized that effective fault detection techniques can help semiconductor manufacturers reduce scrap, increase equipment uptime, and reduce the usage of test wafers. Traditional univariate statistical process control charts have long been used for fault detection. Recently, multivariate statistical fault detection methods such as principal component analysis (PCA)-based methods have drawn increasing interest in the semiconductor manufacturing industry. However, the unique characteristics of the semiconductor processes, such as nonlinearity in most batch processes, multimodal batch trajectories due to product mix, and process steps with variable durations, have posed some difficulties to the PCA-based methods. To explicitly account for these unique characteristics, a fault detection method using the k-nearest neighbor rule (FD-kNN) is developed in this paper. Because in fault detection faults are usually not identified and characterized beforehand, in this paper the traditional kNN algorithm is adapted such that only normal operation data is needed. Because the developed method makes use of the kNN rule, which is a nonlinear classifier, it naturally handles possible nonlinearity in the data. Also, because the FD-kNN method makes decisions based on small local neighborhoods of similar batches, it is well suited for multimodal cases. Another feature of the proposed FD-kNN method, which is essential for online fault detection, is that the data preprocessing is performed automatically without human intervention. These capabilities of the developed FD-kNN method are demonstrated by simulated illustrative examples as well as an industrial example.