In many industry Internet of Things applications, resources like CPU, memory, and battery power are limited and cannot afford the classic cryptographic security solutions. Silicon physical unclonable function (PUF) is a lightweight security primitive that exploits manufacturing variations during the chip fabrication process for key generation and/or device authentication. However, traditional weak PUFs such as ring oscillator (RO) PUF generate chip-unique key for each device, which restricts their application in security protocols where the same key is required to be shared in resource-constrained devices. In this article, in order to address this issue, we propose a PUF-based key sharing method for the first time. The basic idea is to implement one-to-one input–output mapping with lookup table (LUT)-based interstage crossing structures in each level of inverters of RO PUF. Individual customization on configuration bits of interstage crossing structure and different RO selections with challenges bring high flexibility. Therefore, with the flexible configuration of interstage crossing structures and challenges, crossover RO PUF can generate the same shared key for resource-constrained devices, which enables a new application for lightweight key sharing protocols.

Physical Unclonable Function-Based Key Sharing via Machine Learning for IoT Security

Pseudorandom number generators (PRNGs) play a pivotal role in generating key sequences of cryptographic protocols. Among different schemes, a simple chaotic PRNG (CPRNG) exhibits the property of being extremely sensitive to the initial seed and, hence, unpredictable. However, CPRNG is vulnerable if the initial seed is compromised. In this brief, we propose a novel physical unclonable function-based CPRNG (PUF-CPRNG), where the initial seed is secured by generating it from PUF. Furthermore, the proposed PUF-CPRNG includes dynamic refreshing logic to ensure that the random numbers generated are nonperiodic. To further secure the PUF-CPRNG, the feedback values of CPRNG are fed from PUF. An hardware architecture for the proposed methodology has been designed, and the proof of concept implementation was carried out using Xilinx Virtex-7 field-programmable gate array (FPGA). The proposed PUF-CPRNG passes the statistical test NIST 800-22, ENT, and correlation analysis.

PUF-Based Secure Chaotic Random Number Generator Design Methodology

Recently, code reuse attacks (CRAs), such as return-oriented programming (ROP) and jump-oriented programming (JOP), have emerged as a new class of ingenious security threatens. Attackers can utilize CRAs to hijack the control flow of programs to perform malicious actions without injecting any codes. Many defenses, classed into software-based and hardware-based, have been proposed. However, software-based methods are difficult to be deployed in practical systems due to high performance overhead. Hardware-based methods can reduce performance overhead but may require extending instruction set architectures (ISAs) and modifying compiler or suffer the vulnerability of key leakage. To tackle these issues, this paper proposes a new hardware-based control flow checking method to resist CRAs with negligible performance overhead without extending ISAs, modifying compiler and leaking the encryption/decryption key. The key technique involves two control flow checking mechanisms. The first one is the encrypted Hamming distances (EHDs) matching between the physical unclonable function (PUF) response and the return addresses, which prevents attackers from returning between gadgets so long as the PUF response is secret, thus resisting ROP attacks. The second one is the liner encryption/decryption operation (XOR) between PUF response and the instructions at target addresses of call and jmp instructions to defeat JOP attacks. Advanced return-based full-function reuse attacks will be prevented with the dynamic key-updating method. Experimental evaluations on benchmarks demonstrate that the proposed method introduces negligible 0.95% run-time overhead and 0.78% binary size overhead on average.

HCIC: Hardware-assisted Control-flow Integrity Checking

A PUF-based and cloud-assisted lightweight authentication for multi-hop body area network

Traditional username and password-based single-factor authentication is easy to deploy but vulnerable to dictionary attacks, snooping, and brute force attacks. Two-factor authentication (2FA) has been proposed to improve the security, where smart devices are used as the second authentication factor. However, the interaction between human and the smart device is required, which is inconvenient to users. In addition, an attacker is able to get the second authentication factor through fraud, thus invalidating current 2FA mechanisms. In order to solve these problems, we propose a transparent two-factor authentication (T2FA) based on physical unclonable function (PUF) and voiceprint. The second authentication authenticates the user’s mobile phone through the PUF. The third one is to determine whether the login terminal and the user’s mobile phone are in the same environment with the environment voiceprint. The second and third authentication in the second factor is completely transparent to users. Therefore, T2FA avoids the tedious interaction and provides the same high user experience satisfaction as the single-factor authentication and exhibits high security simultaneously. Moreover, the fraud is eliminated technically due to the transparency of the authentication.

T2FA: Transparent Two-Factor Authentication

Ring Oscillator (RO) Physical Unclonable Function (PUF) is one of the most popular silicon PUFs which exploit manufacturing variations during the chip fabrication process. RO PUF can generate secret bits by comparing the frequency difference between two ROs. However, previous RO PUFs improve flexibility and reliability through adding redundant ROs and thus incur unacceptable hardware overheads. In this work, we propose a crossover RO PUF to improve flexibility and reliability and reduce hardware overheads. The basic idea is to implement one-to-one input-output mapping with Lookup Table (LUT)-based interstage crossing structure in each level of inverters. Experimental results show that our proposed structure has much lower hardware overheads and better uniqueness and reliability than the previous configurable RO PUFs. In addition, individual customization on configuration bits of interstage crossing structure and different RO selections by challenges bring high flexibility.

Crossover Ring Oscillator PUF

Chip layer assignment is a key step in analytical placement of 3D ICs. Analytical placement should face the conversion from 3D continuous space in z-direction to several connected 2D chip layer spaces by layer assignment. However, layer assignment may destroy the previous optimal solution in 3D continuous space. To smooth the transition from an optimal 3D placement to a legalized, layer-assigned placement, this paper proposes a layer assignment method using the minimum cost flow, which protects solution space and inherits optimal wirelength at most. We embody this layer assignment method in a multilevel non-linear placement of 3D ICs that minimizes a weighted sum of total wirelength and TSVs number subject to area density constraints. Compared to the recently published 3D placement method [2] [7], this placement algorithm can achieve better wirelength results.

http://or.nsfc.gov.cn/bitstream/00001903-5/417862/1/1000004117552.pdf

Chip layer assignment method for analytical placement of 3D ICs

With the rapid increase of scale in IC design, the large scale IC placement has become more and more important. After global distribution and some objectives optimized, legalization is a core task to remove the overlap, align cells to sites, and try to preserve the optimal solution from global placement simultaneously. As we know, in large scale IC design, blind alignment will damage global placement solution and increase the wire length greatly. In nowadays research, cells managing order is often underemphasized and most of the legalizers choose the natural cells ordering. However, it is observed that a good choice of managing order would be beneficial for the placement solution. In this paper, a wire length driven legalization for standard cells is proposed, which guides cells distribution with different managing ordering in different stages and optimizes wire length by subsection optimization. In addition, a bounding box is built to narrow the searching area of optimal position in invalid cell instances relocation stage. Experimental results show that our legalizer gets 8% of the average wire length reduction over FastPlace3.0 (Agnihorti et al., 2003) on the ISPD2005 benchmarks.

http://ieeexplore.ieee.org/iel7/6747110/6765270/06765396.pdf

An effective legalization approach based on multiple ordering

The executing analytical global placers on a flat cell design might give the best placement results, but nevertheless can incur extremely long runtime, especially when the scale of netlists is increasing dramatically nowadays. And in the flatten mode experiments, the results reveal some unexpected situations like several cells with same logical connections are inseparable. Clustering offers an aviliable solution to above questions and give an attractive choice to reduce the scale and complexity of the design, at the same time improve the placement quality. In this paper, we present a new cluster technique called DyadicCluster to consider the internal and external connections between two cells and add the area constraints, so as to combine the most closely two cells, which is more quick and accurate than previous methods. DyadicCluster has been embedded into the global placement process of a nonlinear placer DCNP for large-scale designs. The DCNP runtime explicitly decreases compared to the flatten mode [1] by 40% and the quality improves by 12%. And the half-perimeter wirelength of our placer after detail placement outperforms current state-of-the-art placers Capo, FastPlace, Fengshui and mPL5-fast by 7%, 9%, 1%, and 5% respectively.

A DyadicCluster method used for nonlinear placement

Uniform granularity design style is widely used in FPGA and structure ASIC designs, which have been dramatically developed in various electronic product fields due to their fast implementation and short time-to-market. Under very deep sub-micron technology nodes, placement becomes a key part of such design style especially in FPGA designs because it affects the following routing efficiency and the final resource requirements very much. At present, the commonly used placement methods are based on the Simulated Annealing. But such kinds of algorithms take too much run time. In this paper, a nonlinear placement technique is proposed to handle the uniform granularity based placement problem, which is especially useful for FPGA placement. In comparison with general nonlinear placement techniques, this technique takes less solving iterations and run-time since the problem has more smooth solution space, and the experimental results compared to FastPlace also show its reasonable quality.

Xu Qian

Papers

Crossover Ring Oscillator PUF

Chip layer assignment method for analytical placement of 3D ICs

An effective legalization approach based on multiple ordering

A DyadicCluster method used for nonlinear placement

A nonlinear placement technique for FPGA-like uniform granularity problem