This paper presents a low power, ultrahigh-speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse sine-weighted DAC and eight 3-bit fine sine-weighted DACs, the core area of the DDS is 3 × 2.5 mm2. The maximum clock frequency was measured at 8.6 GHz with a 4.2958 GHz output. The DDS consumes 4.8 W of power using a single 3.3 V power supply. It achieves the best reported phase and amplitude resolutions, as well as a leading power efficiency figure-of-merit (FOM) of 81.1 GHz·2SFDR/6/W in the mm-wave DDS design. The measured spurious-free-dynamic-range (SFDR) is approximately 45 dBc with a 4.2958 GHz Nyquist output, and 50 dBc with a 4.2 MHz output in the Nyquist band at the maximum clock frequency of 8.6 GHz. Under a 7.2 GHz clock input, the worst-case Nyquist band SFDR and narrow band SFDR are measured as 33 dBc and 42 dBc respectively. The measured phase noise with an output frequency of 1.57 GHz is - 118.55 dBc/Hz at a 10 kHz frequency offset with a 7.2 GHz clock input generated from an Agilent E8257D analog signal generator. All the measurements were taken with the chips bonded in a CLCC-52 package.

An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC

This paper presents a low-power direct digital frequency synthesizer (DDFS) based on a hybrid design with a maximum operating frequency of 1.3 GHz. The proposed hybrid design is capable of extending the resolution of traditional nonlinear digital-to-analog converter (DAC)-based DDFS by adding a linear slope component to the approximated sine wave produced from a nonlinear DAC via an additional linear DAC. With an 11-bit combined DAC, the prototype DDFS produces a minimum spurious free dynamic range (SFDR) of 52 dBc from dc up to Nyquist frequency when clocked at 1.3 GHz. This 90-nm CMOS chip occupies 2 mm2 including bond pads and dissipates 350 mW with a 1.2-V digital supply and 2.5-V analog supply. The FOM of this chip is measured at 1207.9 GHz ·2 ENOB /W .

A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS

This paper presents a 12 GHz direct digital synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 mum SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current-steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of the DDS MMIC is measured as 11.9 GHz at the Nyquist output and 12.3 GHz at 2.31 GHz output. The spurious-free dynamic range (SFDR) of the DDS, measured at Nyquist output with an 11.9 GHz clock, is 22 dBc. The power consumption of the DDS MMIC measured at a 12 GHz clock input is 1.9 W with dual power supplies of 3.3 V/4 V. The DDS thus achieves a record-high power efficiency figure of merit (FOM) of 6.3 GHz/W. With more than 9600 transistors, the active area of the MMIC is only 2.5 x 0.7 mm2. The chip was measured in packaged prototypes using 48-pin ceramic LCC packages.

A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 $\mu$ m SiGe BiCMOS Technology

Using a 3.5 $micro;m gate length complementary metal-oxidesemiconductor/silicon-on-sapphire (CMOS/80S) technology, a singlechip, radiation-hardened, direct digital frequency synthesizer has been developed. The circuit is a critical component of a fast-tuning wideband frequency synthesizer for spread spectrum satellite communications. Each clock period, the chip generates a new digitized sample of a sine wave, whose frequency is variable in 2 20 steps from dc to one-half the clock frequency. Operation at up to 7.5 MHz is possible in a worst case environment, including ionizing radiation levels up to 3 x 10 5 rads(Si). A computationally efficient algorithm was chosen, resulting in 12-bit output precision with only 1084 logic gates and 3840 bits of on-chip read-only memory (ROM). The accuracy of the algorithm is sufficient to maintain in-band spurious frequency components below ??-??65 dDc. At 300 mW, the chip replaces an MSI implementation which uses 25 integrated circuits and consumes 3.5 W.

CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Spectrum Communications

A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This letter discusses the BiCMOS design improvements used for the phase accumulator and the phase-to-amplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-level BiCMOS logic, and the phase-to-amplitude conversion is completed through a bipolar differential pair. The circuit has been processed in a BiCMOS SiGe:C 0.25 mum technology. The power consumption is 308 mW and it operates from a 2.8 V supply. The chip core area is 1 mm2.

/pdf/a-6-ghz-low-power-bicmos-sige-c-0-25-mu-m-direct-digital-4506wtgf5h.pdf

A 6-GHz Low-Power BiCMOS SiGe:C 0.25 $\mu$ m Direct Digital Synthesizer

This paper describes a 9-bit 6.2-GHz low power quadrature direct digital synthesizer (DDS) implemented in a 0.18-mum SiGe BiCMOS technology. With a 9-bit pipeline accumulator and two 8-bit sine-weighted current steering DACs, this DDS is capable of generating quadrature sinusoidal waveforms up to 3.15 GHz with a maximum clock frequency of 6.2 GHz. Packed with more than 13 500 transistors, the quadrature DDS occupies an active area of 2.3 times 2.5 mm2 and a total die area of 3.0 times 3.0 mm2. The measured spurious-free dynamic range is approximately 26 dBc at a clock frequency 6.2 GHz. At the maximum clock frequency, the power consumption of the DDS is 2.5 W with 3.3- and 4.0-V power supplies for the digital and analog parts, respectively. The DDS thus achieves a power efficiency figure-of-merit of 5.04 GHz/W/phase. The DDS chips were packaged with 48-pin ceramic leadless chip carriers and air cooling was used during the measurement.

/pdf/a-9-bit-quadrature-direct-digital-synthesizer-implemented-in-ri9ojnt00z.pdf

A 9-bit Quadrature Direct Digital Synthesizer Implemented in 0.18- $\mu{\hbox {m}}$ SiGe BiCMOS Technology

This paper presents a 2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). A nonlinear current steering digital to analog converter (DAC) has been utilized to convert phase word to sine wave amplitude directly without area consuming ROM for the sine look-up table, which is the speed bottleneck of the DDFS circuit. In order to achieve high speed performance and low power dissipation, CMOS current mode logic (CML) is chosen to implement the logic cells. A semi-symmetrical switching scheme of current source matrix of the nonlinear DAC is proposed to compensate the systematic and gradient errors introduced by the processing and environment variations. The DDFS chip is implemented in Chartered 0.35 /spl mu/m CMOS technology with die area of 2.1/spl times/1.9 mm/sup 2/ and total power consumption of 820 mW at 3.3 V supply voltage.

https://www.eng.auburn.edu/~daifa01/Top/PubPapers/2002-2005/cfpaper2005-02.pdf

2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer

This paper presents a low power, high speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse DAC and seven 3-bit fine DACs, the core area of the DDS is 3 times 2.5 mm2. The maximum clock frequency was measured at 8.6 GHz with 4.2958 GHz output. The DDS consumes a power of 4.8 W under a 3.3 V power supply. It achieves the best reported phase and amplitude resolutions and the best power efficiency figure of merit (FOM) 182 GHz ldr 2ENOB/W. The measured SFDR is approximately 40 dBc with 4.2958 GHz Nyquist output and 48 dBc with 4.2 MHz output at the maximum clock frequency of 8.6 GHz. The chip was measured using LCC-52 packages.

An 11-bit 8.6GHz direct digital synthesizer MMIC with 10-bit segmented nonlinear DAC

A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC The ADC-DAC RFIC is implemented in a 012 mum SiGe technology and occupies an area of 15 times 17 mm2 The total power consumption for the entire ADC-DAC chip is 236 W with a 42 V power supply The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 305 dBc and a peak effective number of bits (ENOB) of 28 bits at a 20 GS/s sampling rate

Xuefeng Yu

Papers

A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 $\mu$ m SiGe BiCMOS Technology

A 9-bit Quadrature Direct Digital Synthesizer Implemented in 0.18- $\mu{\hbox {m}}$ SiGe BiCMOS Technology

2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer

An 11-bit 8.6GHz direct digital synthesizer MMIC with 10-bit segmented nonlinear DAC

A 3-bit 20GS/s interleaved flash analog-to-digital converter in SiGe technology