Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six-transistor (6T) SRAM and proposes an alternative bitcell that functions too much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip.

A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be designed for exceptional stability and write margins, array-level implications must also be considered to achieve a viable memory solution. These constraints can be addressed by modifying traditional 6T-SRAM techniques and conceding some design complexity and area penalties. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies. The proposed 8T solution is demonstrated in a high-performance 32 kb subarray designed in 65 nm PD-SOI CMOS that operates at 5.3 GHz at 1.2 V and 295 MHz at 0.41 V.

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. A few general principles are first introduced to gain an insight into the design issues and the approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is accompanied by rigorous analysis for each key concept. The analysis ranges from the circuit to the micro-architectural level, and reference is given to process, physical and system levels when necessary. Among the main goals of this paper, it is shown that many paradigms and approaches borrowed from traditional above-threshold low-power VLSI design are actually incorrect. Accordingly, common misconceptions in the ULP domain are debunked and replaced with technically sound explanations.

Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial

A 256kb sub-threshold SRAM operates below 400mV from 0 to 85degC and is implemented in 65nm CMOS technology. For the same 6sigma static-noise margin, the sub-threshold SRAM at 0.4V achieves 2.25-times lower leakage power and 2.25-times lower active energy than its 6T counterpart at 0.6V. The SRAM uses a 10T bitcell to enable sub-threshold functionality

A 256kb Sub-threshold SRAM in 65nm CMOS

Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.

Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits

To help overcome limits to the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. It consists of seven transistors, several of which are low-Vth nMOS transistors used to achieve both low-VDD and high-speed operations. For the same speed, the area of our proposed SRAM is 23% smaller than that of a conventional SRAM. Further, we have fabricated a 64-kb SRAM macro using 90-nm CMOS technology and have obtained with it a minimum VDD of 440 mV and a 20-ns access time with a 0.5-V supply.

A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications

This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V/sub DD/ and threshold voltage V/sub TH/ in active and standby modes. In the active mode, on the basis of delay monitoring results, either VDD control or VTH control is selected to avoid any oscillation problem between them. In V/sub DD/ control, on the basis of delay monitoring results, VDD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V/sub TH/ control, on the basis of power monitoring results, VTH is adjusted so as to maintain a certain switching current I/sub SW//leakage current I/sub LEAK/ ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I/sub SUBTH/ to substrate current I/sub SUB/) is improved by taking into consideration both the effects of lowering V/sub DD/ and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I/sub SW//ILEAK ratio in the active mode and 2) detect optimum body bias conditions (I/sub SUBTH/=ISUB) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V DD and threshold voltage V TH in active and standby modes. In the active mode, on the basis of delay monitoring results, either V DD control or V TH control is selected to avoid any oscillation problem between them. In V DD control, on the basis of delay monitoring results, V DD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V TH control, on the basis of power monitoring results, V TH is adjusted so as to maintain a certain switching current I SW /leakage current I LEAK ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I SUBTH to substrate current I SUB ) is improved by taking into consideration both the effects of lowering V DD and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I SW /I LEAK ratio in the active mode and 2) detect optimum body bias conditions (I SUBTH = I SUB ) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.

Latch circuits have advantage for timing and are widely used for high-speed custom circuits. However, ASIC design flows are based on the circuits with flip-flops. Then, ASIC designers don't use latches. This paper describes a new timing optimization algorithm for ASIC by replacing flip-flops to latches without changing the functionality of the circuits. After latch replacement, restricted retiming called fixed-phase retiming is carried out for timing optimization by minimizing the impact of clock skew and jitter. The experimental results show that 17% delay improvement of the benchmark circuits is achieved by proposed algorithms.

Timing optimization by replacing flip-flops to latches

A multiplying circuit is able to perform a multiplication of n bits×n bits at a high speed by increasing the speed of the forming process of the partial products so that the delay time may be inhibited from increasing for a large n, and which can inhibit the chip size from becoming large. A 6-bit multiplier (Y1 to Y6) is divided into bit sets each having plural bits. The thus divided sets are inputted respectively into booth decoders 1A to 1C to generate three-bit interim outputs m1 to m3. On the other hand, partial product generating circuits 2A, 2B and 2C receive a multiplicand X of plural bits to form partial products p1, p2 and p3 respectively by multiplying the multiplicand X with the interim outputs m1, m2 and m3. These partial products p1 to p3 are transformed in a first full adder allay 3 into interim sums r1 and r2. The thus formed interim sums r1 and r2 are added in a second full adder allay 4 with a value. "s" which is prepared by arranging the lowest bits of the interim outputs m1, m2 and m3 by every other bits with "0" therebetween. The thus formed interim sums are defined as r3 and r4. An adder 5 adds up these interim sums r3 and r4 to provide a multiplication output.

Y. Hagihara

Papers

A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

Timing optimization by replacing flip-flops to latches

Booth's multiplying circuit