General purpose computing on graphical processing units (GPGPU) is a paradigm shift in computing that promises a dramatic increase in performance. GPGPU also brings an unprecedented level of complexity in algorithmic design and software development. In this paper, we present an efficient parallel fault simulator, FSimGP2, that exploits the high degree of parallelism supported by a state-of-the-art graphic processing unit (GPU) with the NVIDIA compute unified device architecture. A novel 3-D parallel fault simulation technique is proposed to achieve extremely high computation efficiency on the GPU. Global communication is minimized by concentrating as much work as possible on the local device's memory. We present results on a GPU platform from NVIDIA (a GeForce GTX 285 graphics card) that demonstrate a speedup of up to 63× and 4× compared to two other GPU-based fault simulators and up to 95× over a state-of-the-art algorithm on conventional processor architectures.

3-D Parallel Fault Simulation With GPGPU

In this paper, we explore the implementation of fault table generation on a Graphics Processing Unit (GPU). A fault table is essential for fault diagnosis and fault detection in VLSI testing and debug. Generating a fault table requires extensive fault simulation, with no fault dropping, and is extremely expensive from a computational standpoint. Fault simulation is inherently parallelizable, and the large number of threads that a GPU can operate on in parallel can be employed to accelerate fault simulation, and thereby accelerate fault table generation. Our approach, called GFTABLE, employs a pattern parallel approach which utilizes both bit-parallelism and thread-level parallelism. Our implementation is a significantly modified version of FSIM, which is pattern parallel fault simulation approach for single core processors. Like FSIM, GFTABLE utilizes critical path tracing and the dominator concept to reduce runtime. Further modifications to FSIM allow us to maximally harness the GPU's huge memory bandwidth and high computational power. Our approach does not store the circuit (or any part of the circuit) on the GPU. Efficient parallel reduction operations are implemented in our implementation of GFTABLE. We compare our performance to FSIM*, which is FSIM modified to generate a fault table on a single core processor. Our experiments indicate that GFTABLE, implemented on a single NVIDIA Quadro FX 5800 GPU card, can generate a fault table for 0.5 million test patterns on average 15.68× faster when compared with FSIM*. With the NVIDIA Tesla server, our approach would be potentially 89.57× faster.

Fault Table Computation on GPUs

The method and device are applied to a parallel computer which carries out parallel processing by transmitting and receiving messages among a plurality of processors. In a memorizing step (50), various pieces of information are memorized such as an execution starting time, standby starting time for waiting for reception of the message, message number on reception of the message, processor number of the processor, the message and time when the message is received, message number on transmitting the message and message execution ending time. In a step of obtaining the maximum delay path, a last ending processor is identified in which execution was last ended, and the standby starting time for waiting reception of the message in the last ending processor, the message number of the last ending processor, the transmitting processor number and the message transmitting processor corresponding to the transmitting processor number are all searched for among the memorized information. These searches are repeated from the last ending processor to a starting processor where execution of the parallel processing was started. Thus, the maximum delay path can be obtained, allowing recognition of where increased data transmission speed is needed.

Performance evaluation method and device thereof for a parallel computer

In this paper, we explore the implementation of fault table generation on a Graphics Processing Unit (GPU). A fault table is essential for fault diagnosis and fault detection in VLSI testing and debug. Generating a fault table requires extensive fault simulation, with no fault dropping, and is extremely expensive from a computational standpoint. Fault simulation is inherently parallelizable, and the large number of threads that a GPU can operate on in parallel can be employed to accelerate fault simulation, and thereby accelerate fault table generation. Our approach, called GFTABLE, employs a pattern parallel approach which utilizes both bit-parallelism and thread-level parallelism. Our implementation is a significantly modified version of FSIM, which is pattern parallel fault simulation approach for single core processors. Like FSIM, GFTABLE utilizes critical path tracing and the dominator concept to reduce runtime. Further modifications to FSIM allow us to maximally harness the GPU's huge memory bandwidth and high computational power. Our approach does not store the circuit (or any part of the circuit) on the GPU. Efficient parallel reduction operations are implemented in our implementation of GFTABLE. We compare our performance to FSIM*, which is FSIM modified to generate a fault table on a single core processor. Our experiments indicate that GFTABLE, implemented on a single NVIDIA GeForce GTX 280 GPU card, can generate a fault table for 0.5 million test patterns on average 7.85x faster when compared with FSIM*. With the NVIDIA Tesla server, our approach would be potentially 34.82x faster.

Fault table generation using Graphics Processing Units

: The primary purpose of this report is to determine the state-of-the-art for fault simulators which are used to estimate the test coverage for the DUT. It is envisioned that the state-of-the-art survey will be used to assist in defining the fault simulation techniques which are applicable to VHDL models. The goal is to fully understand the current fault simulation state-of-the-art so that existing techniques can be used to assist in the design of a VHDL-based fault simulation tool. One attribute which defines a VHDL-based simulator is that a VHDL compliant simulator is used to simulate the faulty device. Hierarchical serial fault simulation and hierarchical concurrent fault simulation are two techniques which can be used to develop a VHDL-based fault simulator. The state-of-the-art for fault grading techniques along with an overview of TPG methods is also provided in this report. While fault simulation is the main focus of this report, fault grading and TPG are included to completely describe the test generation, fault simulation, and fault grading process. It is important to realize that fault simulation is a means to assist TPG and estimate fault coverage via fault grading. The desired goal for a tool set is to contain a fault simulation technique which seamlessly augments the TPG process and performs fault grading in an efficient fashion.

A Survey of Fault Simulation, Fault Grading and Test Pattern Generation Techniques with Emphasis on the Feasibility of VHDL Based Fault Simulation

A fault simulation method called the fault information tracing (FIT) algorithm is presented. Although the basic concept is similar to that of the critical path tracing (CPT) method, which traces sensitive inputs backward to directly determine the fault detectability, FIT is a multiple fault propagation method which considers propagation of all possible stuck-at faults between a gate input and output. Moreover, FIT manages a 'fault information flag' which represents both fault detectability and circuit topology between the current line and a primary output. Use of the fault information flag makes it possible to greatly reduce reconvergent fanout stem analysis. Consequently, exact and efficient simulation is achieved with near linear time complexity. The FIT algorithm is described and results are presented. In addition, the FIT procedure consists of simple propagation of fault information flags between logic gates, which enable implementation on parallel processors. Its suitability for parallel processors. Its suitability for parallel processing is discussed. Moreover, a parallel fault simulation method for AAP2, a massively parallel processor system containing 65536 processing elements, is described. >

Y. Kitamura

Papers

Exact critical path tracing fault simulation on massively parallel processor AAP2