Proceedings ArticleDOI
Exact critical path tracing fault simulation on massively parallel processor AAP2
Y. Kitamura
- pp 474-477
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TLDR
A fault simulation method called the fault information tracing (FIT) algorithm is presented, a multiple fault propagation method which considers propagation of all possible stuck-at faults between a gate input and output and its suitability for parallel processors is discussed.Abstract:
A fault simulation method called the fault information tracing (FIT) algorithm is presented. Although the basic concept is similar to that of the critical path tracing (CPT) method, which traces sensitive inputs backward to directly determine the fault detectability, FIT is a multiple fault propagation method which considers propagation of all possible stuck-at faults between a gate input and output. Moreover, FIT manages a 'fault information flag' which represents both fault detectability and circuit topology between the current line and a primary output. Use of the fault information flag makes it possible to greatly reduce reconvergent fanout stem analysis. Consequently, exact and efficient simulation is achieved with near linear time complexity. The FIT algorithm is described and results are presented. In addition, the FIT procedure consists of simple propagation of fault information flags between logic gates, which enable implementation on parallel processors. Its suitability for parallel processors. Its suitability for parallel processing is discussed. Moreover, a parallel fault simulation method for AAP2, a massively parallel processor system containing 65536 processing elements, is described. >read more
Citations
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Journal ArticleDOI
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Fault Table Computation on GPUs
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Proceedings ArticleDOI
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A Survey of Fault Simulation, Fault Grading and Test Pattern Generation Techniques with Emphasis on the Feasibility of VHDL Based Fault Simulation
TL;DR: The goal is to fully understand the current fault simulation state-of-the-art so that existing techniques can be used to assist in the design of a VHDL-based fault simulation tool.
References
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Journal ArticleDOI
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Proceedings ArticleDOI
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A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor
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