Compact-modeling principles and solutions for nanoscale double-gate and gate-all-around MOSFETs are explained The main challenges of compact modeling for these devices are addressed, and different approaches for describing the electrostatics, the transport mechanisms, and the high-frequency behavior are explained Several approximations used to derive analytical solutions of Poisson's equation for doped and undoped devices are discussed, and the need for self-consistency with Schrodinger's equation and with the current continuity equation resulting from the transport models is addressed Several techniques to extend the compact modeling to the high-frequency regime and to study the RF performance, including noise, are presented and discussed

Compact-Modeling Solutions For Nanoscale Double-Gate and Gate-All-Around MOSFETs

Optimum design of input matching network of CMOS low-noise amplifiers (LNAs) for low-power applications is discussed in this paper. This is done through an investigation of the effect of four different matching methodologies on the gain of radio frequency CMOS LNAs by means of compact analytical expressions. It is demonstrated that methods that convert the MOSFET's input impedance to 50 Omega for power matching are more suitable for low-power applications than methods that create a real 50-Omega resistance at the input of the LNA, such as source inductive degeneration. As it is analytically shown, this is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET's input resistance. The impact of each matching methodology on the noise figure (NF) of the LNA is also discussed in detail and design guidelines for optimum gain-NF performance are developed using analytical models of MOSFET's noise parameters. It is demonstrated that all four methods could achieve very good NF values, provided that the size of active and passive components are chosen carefully based on the given guidelines. Measured results of two monolithic 5.7-GHz LNAs, designed and fabricated in a 0.18-mum CMOS technology, are also presented. The input matching networks of these LNAs are optimized for low-power operation based on the theory presented in this paper. It is experimentally shown that this optimization results in approximately 60% reduction in the dc power consumption and up to 300% improvement in the overall performance of the LNA when compared with some of the most recently published LNAs

Design of the Input Matching Network of RF CMOS LNAs for Low-Power Operation

The simple noise models of field effect and bipolar transistors reviewed in this article are quite useful in engineering practice, as illustrated by measured and modeled results. The exact and approximate expressions for the noise parameters of FETs and bipolar transistors reveal certain common noise properties and some general noise properties of both devices. The usefulness of these expressions in interpreting the dependence of measured noise parameters on frequency, bias, and temperature and, consequently, in checking of consistency of measured data has been demonstrated.

Interpreting Transistor Noise

The purpose of this paper is to address the issues of deembedding multigigahertz CMOS measurements by extensively comparing six popular methods and by proposing a new method based on two-port measurements. The comparison aims to evaluate the maximum applicable frequency of equivalent-circuit methods (open-short, three step, ...) and the effect of the source dangling leg of MOSFETs on the cascade methods (two line and thru). Fifty dummy structures and 12 MOSFETs were fabricated using standard 0.18-mum CMOS technology. It was found that, at low frequencies (<6 GHz), all method results were comparable. The open-short method performed well over the entire frequency range (0.1-40 GHz) studied. The newly developed method, called the thru-short method, uses only two dummy structures, a thru and a short, to completely deembed the parasitics from probe pads, interconnects, and the semiconducting substrate. The measurements validated the thru-short algorithm and showed its usefulness for multigigahertz on-wafer CMOS measurements.

On the Deembedding Issue of CMOS Multigigahertz Measurements

In this letter, it is proposed that gm 2/ID, which has been used as the figure of merit (FoM) of MOSFETs for analog amplifiers, can also be used as the RF MOSFET FoM for optimizing low-noise amplifier (LNA) performance. From a simple small-signal equivalent circuit, signal gain, noise figure, and power consumption equations are derived analytically and verified with the measurement results of the fabricated LNA. The proposed gm 2/ID predicts the optimal bias point for the maximum LNA performance.

A Simple Figure of Merit of RF MOSFET for Low-Noise Amplifier Design

Compact modeling of the most important high-frequency (HF) noise sources of the MOSFET is presented in this paper, along with challenges in noise measurement and deembedding of future CMOS technologies. Several channel thermal noise models are reviewed and their ability to predict the channel noise of extremely small devices is discussed. The impact of technology scaling on noise performance of MOSFETs is also investigated by means of analytical expressions. It is shown that the gate tunneling current has a significant impact on MOSFETs noise parameters, especially at lower frequencies. Limitations of some commonly used noise models in predicting the HF noise parameters of modern MOSFETs are addressed and methods to alleviate some of the limitations are discussed

Y. Kiyota

Papers

High-Frequency Noise of Modern MOSFETs: Compact Modeling and Measurement Issues