Y
Y. Le Cun
Researcher at AT&T
Publications - 6
Citations - 566
Y. Le Cun is an academic researcher from AT&T. The author has contributed to research in topics: Image segmentation & Image processing. The author has an hindex of 5, co-authored 6 publications receiving 536 citations.
Papers
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Journal ArticleDOI
Original approach for the localisation of objects in images
R. Vaillant,C. Monrocq,Y. Le Cun +2 more
TL;DR: An original approach is presented for the localisation of objects in an image which approach is neuronal and has two steps and is applied to the problem of localising faces in images.
Proceedings ArticleDOI
Global training of document processing systems using graph transformer networks
TL;DR: A new machine learning paradigm called Graph Transformer Networks is proposed that extends the applicability of gradient-based learning algorithms to systems composed of modules that take graphs as inputs and produce graphs as output.
Proceedings Article
An original approach for the localization of objects in images
R. Vaillant,C. Monrocq,Y. Le Cun +2 more
TL;DR: In this article, the authors presented an algorithm for the detection of faces in images using shared-weight replicated neural networks, where a neural net forms rough hypotheses about the position of faces and then verified these hypotheses using a second neural network.
Proceedings ArticleDOI
Browsing through high quality document images with DjVu
TL;DR: Presents a new image compression technique called DjVu that is specifically geared towards the compression of high-resolution, high-quality images of scanned documents in color, and is available as a plug-in for popular Web browsers.
Proceedings ArticleDOI
Hardware requirements for neural-net optical character recognition
Lawrence D. Jackel,Bernhard E. Boser,John S. Denker,Hans Peter Graf,Y. Le Cun,Isabelle Guyon,D. Henderson,Richard Howard,W. Hubbard,Sara A. Solla +9 more
TL;DR: An advanced (and working) reconfigurable neural-net chip that mixes analog and digital processing is described, and within this framework, it is possible to design chips that have broad utility, large connection capacity, and high speed.