This brief investigates a switched-capacitor (SC) second-order delta-sigma modulator using integrator multiplexing with respect to component imperfections. The two integration operations, which are characteristic for a second-order system are accomplished by multiplexing two integration capacitors CU and CV onto a single operational amplifier. The two feedback loops are implemented utilizing two capacitors CA and CB, which are charged and discharged periodically. Crosstalk between the two integration capacitors CU and CV due to parasitic capacitances introduces additive white noise. However, the influence can easily be limited using standard SC technology. A mismatch between CA and CB introduces a dc-offset and a gain error, as derived quantitatively. As a consequence, the robustness to component imperfections, which is typical for second-order delta-sigma modulators, is maintained. It is shown that in principle, integrator multiplexing can be generalized for higher order delta-sigma modulators

Analysis of a Switched-Capacitor Second-Order Delta&#8211;Sigma Modulator Using Integrator Multiplexing

On complex system-on-chips (SOCs), a compact on-die analog-to-digital converter (ADC) is required in high-volume testing, in order to reduce the test time and improve the test coverage of on-die analog intellectual properties (IPs). This paper presents a compact first-order ${\Sigma\Delta }$ modulator for on-die voltage measurements in such applications. The primary design focus is to achieve a highly compact area so that many instances can be integrated to cover the testing of multiple analog IPs on a single chip die. The proposed modulator deploys an inverter-based architecture which enables the aggressive area reduction. There are two new additional enhancements: 1) hardware dithering to minimize the limit-cycling effect and 2) time-multiplexed pseudodifferential operation for common mode rejection. The modulator exhibits a figure of merit (FOM) of 554.7 fJ/conv-step, in spite of the compact area of only ${0}.{00023}\;{\text{mm}}^{2}$ .

A Compact First-Order $\Sigma\Delta $ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process

A novel third order delta sigma modulator (DSM) is presented. The third order loop filter in the proposed DSM shares one opamp among three integrator stages through an optimal operation timing, which makes use of load capacitance differences between integrator stages. The power dissipation of the proposed DSM is much lower than conventional third order DSM because power consuming blocks in the DSM are only one opamp and a comparator. The proposed DSM, designed on 0.35µm CMOS process under 3.3V supply achieves 1mW power dissipation with 100-11kHz band width and 96dB SQNR.

A novel third order Delta Sigma Modulator with one opamp shared among three integrator stages

An energy-efficient ΔΣ modulator has been investigated by using dynamic-common-source integrators. Instead of the virtual short commonly used in conventional opamp-based integrators, the novel integrator used the fact that when a MOSFET turns off from its on-state, the voltage difference between the gate and source approaches to the threshold voltage, which is virtually constant after the charge redistribution. No static currents flow in the present integrator, resulting in high energy efficiency. An FOM of 29 fJ/comv-step was estimated by our transistor-level circuit simulation assuming a 0.18-μm standard CMOS technology with an SNDR, a bandwidth and a sampling frequency of 82.6dB, 20 kHz and 5 MHz, respectively.

An Energy-Efficient ΔΣ Modulator Using Dynamic-Common-Source Integrators

The union of signal processing circuitry and transducers -sensors, emitters and actuators -forming integrated transducer systems may provide many benefits. These advantages include increased accuracy, dynamic range, noise immunity, reliability and ease of use in ways not otherwise attainable with discrete systems. This thesis investigates some of the analog signal processing circuits that have applications in the development of integrated transducer systems. Specifically, small low-powered A/D converters using both algorithmic and time-domain conversion methods are presented. In order to achieve the size, power and dynamic range restrictions with a digital IC process, current-mode circuit techniques were employed. One example of integrated transducer systems, known as the visual-tothermal converter cell, was also implemented and evaluated. A single visual-to-thermal converter cell combines a photodetector and a thermal pixel along with a local algorithmic A/D converter operating in the currentdomain. Arrays of these cells would convert a visual scene to a thermal scene with the same resolution. Another integrated transducer system is proposed. This system integrates a MAGFET transducer with signal processing developed in this thesis. The design would provide a single digital signal with a duty cycle related to the incident magnetic flux. Due to the minimal size, power and interconnect requirements, the design has applications in systems requiring arrays of MAGFETs.

http://summit.sfu.ca/system/files/iritems1/5077/b14873503.pdf

Current-mode signal processing for integrated transducer systems

A small-scale sigma-delta modulator for a sigma-delta A/D converter is presented. The proposed modulator employs a double-integration switched-capacitor architecture. The circuit configuration has low sensitivity to the process deviation of analog components. The scale of the circuit is so small because of its use of a time division multiplexed integrator, By means of simulation, the proposed modulator achieves 71.6 dB signal-to-noise ratio and 76.4 dB dynamic range at a sampling rate of 3 MHz. >

An oversampled sigma-delta A/D converter using time division multiplexed integrator

The authors present Bi-CMOS current mode circuits with 1-V supply voltage The circuits are composed of current mirrors, current comparators, and current sources The circuits have advantages such as high accuracy, high speed, high density, and low supply voltage As an application of the circuits, an analog-to-digital converter (ADC) is presented The ADC operates with small chip area and low power dissipation Circuit simulations of the proposed circuits were performed using the SPICE2 program From the SPICE simulation, 6-b resolution, 1-V supply voltage, 5-MHz sampling rate, and 10-mW power dissipation were confirmed >

Y. Ogata

Papers

An oversampled sigma-delta A/D converter using time division multiplexed integrator

Bi-CMOS current mode circuits with 1 V supply voltage and their application to ADC