This paper surveys, reviews, and critiques analytic models of MOSFET short-channel effects (SCEs) in subthreshold published over the past four decades. In the first half of this paper, the published models on SCEs are categorized into the following four main groups based on their approach: 1) charging sharing models; 2) empirical expressions; 3) polynomial potential models; and 4) analytic solutions to 2-D Poisson's equation. The strength and weakness of each approach are elaborated in terms of its physical soundness and predictive ability. A key development was the exponential dependence of SCE on channel length (L) , SCE ~ exp(-L/l0), leading to the introduction of scale length (l0). In the second half of this paper, the predictions of each analytic SCE model are examined by generic 2-D numerical simulations. In particular, the merit of each model is judged by its prediction on the scale length (l0) as a function of the thickness and dielectric constant (κ) of the gate insulator. Only one model, i.e., the generalized scale length model that treated the silicon and insulator regions as two distinct dielectric regions with shared boundary conditions, correctly predicted the MOSFET scale length under all dielectric constant and thickness conditions. A variation of the generalized scale length model applies to recent multiple-gate MOSFETs near the limit of scaling.

Review and Critique of Analytic Models of MOSFET Short-Channel Effects in Subthreshold

As MOS devices are shrunk to near and submicrometer dimensions, short channel, narrow width and small geometry effects cause variations in the threshold voltage. It is critical for circuit and device designers to be able to predict these variations. This paper reviews and compares the various modeling techniques developed to determine the threshold voltage as a function of device geometry. It is hoped this review will provide insights for the development of new models for today's small devices.

Threshold voltage models of short, narrow and small geometry MOSFET's: A review

Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.

Analytical model and characterization of small geometry MOSFET's

This paper describes an approach to reducing short-channel effects in small-dimension MOSFET's, with emphasis focused on the geometrical channel structure along a gate. To minimize threshold-voltage sensitivities, the advantage of an inhomogeneous channel structure with a highly doped region near the source is demonstrated through a theoretical analysis and extensive use of a two-dimensional device simulation. This structure, which can be realized through DSA technology, obtains adequate tolerances for both the channel length and applied drain voltage in the 1-µm channel-length MOSFET; the anticipated channel-length tolerance ( \Delta L ) for maintaining the threshold-voltage fluctuation to within ± 10 percent is estimated to be ± 0.25 µm when V_{d} = 5.0 V and gate-oxide thickness t_{ox} = 30 nm. With this tolerance, threshold sensitivity to drain voltage drops to one-third in a conventional MOSFET. In a 0.5-µm channel-length MOSFET, ( \Delta L ) is estimated to be ± 0.7 µm when V_{d}= 3.0 V.

Threshold-sensitivity minimization of short-channel MOSFET's by computer simulation

This paper describes an explicit manifestation of quantum-mechanical influences on the short channel effects (SCE) in the threshold voltage of ultra-thin buried-channel MOSFET/SIMOX devices. The theoretical model predicts an abnormal quantum mechanical SCE (QSCE) in extremely thin SOI layer. It also predicts that the QSCE becomes much salient at low temperatures, which is examined quantitatively by experiments.

Quantum mechanical influences on short-channel effects in ultra-thin MOSFET/SIMOX devices

A detailed expression of the threshold voltage for a short-channel MOSFET is derived from a model of surface-potential distribution under the gate using a relationship of surface-channel charge neutrality. The theory is compared with the measured threshold voltages. The theoretical curves for threshold voltage over a wide range of drain and backgate voltage are in good agreement with experimental results. It is shown for a MOSFET having a channel length less than 2 μm that the body-bias constant increases as the drain voltage increases. The theory also predicts that the increase in backgate voltage leads to the reduction in short-channel effect for the shorter-channel case.

Y. Ōmura

Papers

Threshold voltage theory for a short-channel MOSFET using a surface-potential distribution model