: The reports contains the results on the process improvements to develop an integrated semiconductor memory utilizing complementary MOS transistors. Various factors which affect process control were investigated. An optimum structure for obtaining complementary regions of p-type and n-type silicon is given. Complementary pairs of normally-off n-channel and p-channel devices were obtained both on separate and on a single substrate material. The cleanliness during the process is an important factor which affects the reproducibility and the uniformity of the device characteristics. (Author)

Mos integrated circuits.

The paper describes a self-biased CMOS transistor circuit with two outputs providing the transistor threshold voltages, V_{TP} and -\,V_{TN}. Both outputs are referenced to the same V_{DD} supply line, and hence, the circuit can be used as a convenient test device. The V_{TP} extractor is based on the “nested” connection of two transistors; the -\,V_{TN} extractor is designed using the difference of gate-source voltages in two different size transistors carrying equal currents. The circuit was realized in 0.8 μm technology, and the results of simulation and experiment are compared. Recommendations to improve the design are given.

Input-Free \bi V_{TP} and -\,\bi V_{TN} Extractor Circuits Realized on the Same Chip

An accurate threshold voltage extraction scheme for MOS transistors is presented. The scheme differs from alternative methods recently reported in the literature in that it does not require matched replica of the transistor under test and thus can be applied more effectively and accurately to real-time on-chip applications where threshold voltage measurements are required for many transistors with various geometries and bias conditions. The proposed scheme is accurately implemented in a matching-free way using a ratio-independent switched-capacitor subtracting amplifier and a dynamic current mirror. Nonideal effects associated with these circuits are investigated. >

An accurate and matching-free threshold voltage extraction scheme for MOS transistors

A circuit for the detection of the threshold voltage V/sub TH/ of MOS devices is presented. The basic scheme proposed here is implemented in BiCMOS technology but can also be applied in any standard CMOS process. The deviation of the detected V/sub TH/ from the actual (or extrapolated) one is analytically estimated, taking into account the effects due to channel length modulation and mobility modulation. The results obtained show that the error at ambient temperature is lower than 0.6% for all values of V/sub DD/ larger than 3.25 V, and for temperatures in the range -25 degrees C to 125 degrees C the error is never higher than 4%. >

Accurate MOS threshold voltage detector for bias circuitry

Mutual compensation of mobility and threshold voltage temperature variations may result in a zero temperature coefficient (ZTC) bias point of an NMOS transistor. The conditions under which this effect occurs, stability of this bias point, and the temperature dependence of the output voltage for a diode-connected transistor operating in the vicinity of ZTC point are investigated in this paper. Some possible applications of this effect include temperature sensors with linear dependence of voltage versus temperature, and voltage and current reference circuits. The theory is verified experimentally investigating the temperature behavior of an NMOS transistor realized in 0.35 μm CMOS process. The design and simulation results of simple current and voltage reference circuits for implementation in 0.18 μm CMOS technology are given.

Temperature dependence of output voltage generated by interaction of threshold voltage and mobility of an NMOS transistor

A method is presented for the generation of a voltage equal to an integer multiple of the n-channel threshold voltage in c.m.o.s. integrated circuits. Experimental results from an integrated prototype are given and possible applications are discussed

Y.P. Tsividis

Papers

Threshold voltage generation and supply-independent biasing in c.m.o.s. integrated circuits