Testing asynchronous circuits: a survey

Experiences in Fault Tolerant Computing, 1947-1971.- Evolution of Fault Tolerant Switching Systems in AT&T.- Fault Tolerance in Tandem Computer Systems.- Evolution of Reliable Computing in Hitachi and Autonomous Decentralized System.- A History of Research in Fault Tolerant Computing at SRI International.- The Evolution of Fault Tolerant Computing at the Charles Stark Draper Laboratory, 1955-85.- The Evolution of Fault Tolerant Computing at the Jet Propulsion Laboratory and at UCLA: 1955-1986.- Dependable Computing and Fault Tolerance at LAAS: a Summary.- Reliable Digital Systems and Related Stanford University Research.- Design Fault Tolerance.- The Evolution of Fault Tolerant Computing at the University of Illinois.- The Evolution of Fault Tolerant Computing at the University of Michigan.- Experimental Research in Reliable Computing at Carnegie Mellon University.- A History of Research in Fault Tolerant Computing at the Grenoble University.- Research Activities on FTC in Japan.- The Evolution of Dependable Computing in Italy.- Fault Tolerant Computing Systems in Germany.- The Technical Committee on Fault Tolerant Computing of The IEEE Computer Society.- Biographies.- Author Index.

The evolution of fault-tolerant computing

This paper presents a survey of CMF (common-mode failures) in redundant systems with emphasis on VLSI (very large scale integration) systems. The paper discusses CMF in redundant systems, their possible causes, and techniques to analyze reliability of redundant systems in the presence of CMF. Current practice and results on the use of design diversity techniques for CMF are reviewed. By revisiting the CMF problem in the context of VLSI systems, this paper augments earlier surveys on CMF in nuclear and power-supply systems. The need for quantifiable metrics and effective models for CMF in VLSI systems is re-emphasized. These metrics and models are extremely useful in designing reliable systems. For example, using these metrics and models, system designers and synthesis tools can incorporate diversity in redundant systems to maximize protection against CMF.

Common-mode failures in redundant VLSI systems: a survey

Redundant systems are designed using multiple copies of the same resource (e.g., a logic network or a software module) in order to increase system dependability. Design diversity has long been used to protect redundant systems from common-mode failures. The conventional notion of diversity relies on "independent" generation of "different" implementations. This concept is qualitative and does not provide a basis for comparing the reliabilities of two diverse systems. In this paper, for the first time, we present a metric to quantify diversity among several designs and illustrate its effectiveness using several examples. Applications of this metric in analyzing reliability and availability of diverse redundant systems, and deriving simple relationships between diversity, system failure rate, and mission time are also demonstrated.

A design diversity metric and analysis of redundant systems

Design diversity has long been used to protect redundant systems against common-mode failures. The conventional notion of diversity relies on "independent" generation of "different" implementations. This concept is qualitative and does not provide a basis to compare the reliabilities of two diverse systems. In this paper, for the first time, we present a metric to quantify diversity among several designs. Based on this metric, we derive analytical reliability models that show a simple relationship between design diversity, system failure rate, and mission time. In addition, we present simulation results to demonstrate the effectiveness of design diversity in Duplex and Triple Modular Redundant (TMR) systems. For independent multiple-module failures, we show that, mere use of different implementations does not always guarantee higher reliability compared to redundant systems with identical implementations-it is important to analyze the reliability of redundant systems using our metric. For common-mode failures and design faults, there is a significant gain in using different implementations-however, as our analysis shows, the gain diminishes as the mission time increases. Our simulation results also demonstrate the usefulness of diversity for enhancing the self-testing properties of redundant systems.

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A design diversity metric and reliability analysis for redundant systems

A sequential machine must have certain redundant information in order to be capable of correcting error. As past inputs and past states are redundant, a sequential machine with error correction capability is constructable by making use of these elements of past information. This paper describes conditions of state assignments, numbers of required redundant state variables, and estimation of reliability of failure-tolerant sequential machines.

Failure-Tolerant Sequential Machines with Past Information

The problem of the realization of fail-safe asynchronous sequential circuits was recently studied by Patterson and Sawin. This correspondence presents a different approach to the same subject which, in some cases, yield us simpler realization than those by the methods ever proposed, combining the notion of the ordered partition with Tracey's method for the state assignment of asynchronous sequential circuit.

A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits

A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state when a fault exists is described. Finally, some extensions of the technique are attempted.

Y. Tohma

Papers

Failure-Tolerant Sequential Machines with Past Information

A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits

Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory