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Yan Li

Researcher at Shenzhen University

Publications -  31
Citations -  101

Yan Li is an academic researcher from Shenzhen University. The author has contributed to research in topics: CMOS & Operational amplifier. The author has an hindex of 5, co-authored 28 publications receiving 86 citations.

Papers
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Journal ArticleDOI

Miniature RFID tri-band CPW-fed antenna optimised using ISPO algorithm

TL;DR: In this paper, a tri-band CPW-fed antenna designed for RFID applications is reported, which has four U-shaped, two F-shaped and two L-shaped slots as additional resonators to achieve multi-band operation.
Patent

Parking lot management method and system based on subscriber identity module (SIM)-radio frequency identification (RFID) card in mobile phone

TL;DR: In this paper, a parking lot management method and system based on a SIM-radio frequency identification (RFID) card in a mobile phone is presented, in which a read-write device reads an identity code from the RFID module through a frequency band of 13.56 Mhz and sends the identity code to a central server; the central server identifies the identity codes and opens a gate to let an automobile get into the parking lot; after the automobile is parked at a berth, a positioning device sends position information of the berth to the SIM module and forwards the position information into
Proceedings ArticleDOI

Adaptive Lifting Scheme for ECG QRS complexes detection and its FPGA implementation

TL;DR: An Adaptive Lifting Scheme (ALS) has been developed and successfully implemented in Field Programmable Gate Array (FPGA) and its detection accuracy is higher than 99.681%, fulfilling ECG signal processing requirements.
Journal ArticleDOI

A CMOS Time-to-Digital Converter for Real-Time Optical Time-of-Flight Sensing System

TL;DR: A TDC with ~40 ps measurement resolution and very large linear dynamic range is proposed for optical sensing applications, refereed to a single 100 MHz clock, which incorporates a DLL and a VDL loop to automatically stabilize the measuring resolution, thus eliminating the need for a separate calibration step before or during actual measurements.
Proceedings ArticleDOI

A 31µW ask clock and data recovery circuit for wireless implantable systems

TL;DR: A novel extremely low power receiver designed for such a scheme is discussed and exhibits a sensitivity of ∼1mV at 1.5MHz, covers an input data rate between 7k bit/s and 45.5kbit/s, and consumes only ∼31µW of power.