With the increasing popularity and applications of 2.5-D integration, both chip and packaging industries are making significant progress in this direction. In advanced high-density 2.5-D packages, package redistribution layers become similar to chiplet back-end-of-line routing layers, and the gap between them scales down with pin density improvement. Chiplet–package interactions become significant and severely affect system performance and reliability. Moreover, 2.5-D integration offers opportunities to apply novel design techniques. The traditional die-by-die design approach neither carefully considers these interactions nor fully exploits the cross-boundary design opportunities. In this article, we present a holistic chiplet–package co-optimization flow for high-density 2.5-D packaging technologies with little performance overhead and zero pipeline-depth increase. Our holistic extraction can capture all parasitics from chiplets and the package and improve system performance through iterative optimizations. Both drop-in and pay-as-you-use design methodologies are implemented for agile development and quick turn-around time. To prove the effectiveness of our flow, we implement several design cases of a microcontroller system in TSMC 65-nm technology. Our design methodologies can reduce the performance gap by 85% with respect to the 2-D reference design after holistic optimizations. We demonstrate design flexibility and development cost-saving by presenting several flavors of a three chiplets system. To validate our flow in silicon, we tape-out a chip in TSMC 65-nm technology with measured data and validated functionality.

Holistic Chiplet–Package Co-Optimization for Agile Custom 2.5-D Design

In modern packaging technology, redistribution layers (RDLs) are often used to redistribute interconnections among multiple chips and between I/O pads and bump pads. For high-density RDL routing, irregular vias, where vias can be placed at arbitrary locations, are adopted to better utilize RDL resources to obtain desired routing solutions. As the problem size increases, however, using irregular vias may suffer from high computation overheads. Moreover, most previous works route pre-assignment (PA) and free-assignment (FA) nets in separate stages, incurring routing resource competition. To remedy these disadvantages, we propose a simultaneous PA and FA routing framework with irregular RDL via planning. In this paper, we first propose a novel partitioning method based on the Voronoi diagram to handle irregular via structures and derive a theoretical upper bound on the number of generated regions. We then propose a chord-based tile model and a net-sequence list to generate non-crossing guides for PA and FA nets on the same routing graph. Finally, we develop a novel geometry-based pattern routing to obtain the final solutions. Experimental results show that our work can achieve 100% routability and an average 30X speedup over the-state-of-the-art work.

Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias

In modern VLSI designs, I/O counts have been growing continuously as the system becomes more complicated. To achieve higher routability, the hexagonal array is introduced with higher pad density and a larger pitch. However, the routing for hexagonal arrays is significantly different from that for traditional gird and staggered arrays. In this paper, we consider the Y-architecture-based flip-chip routing used for the hexagonal array. Unlike the conventional Manhattan and the X-architectures, the Y-architecture allows wires to be routed in three directions, namely, 0-, 60-, and 120-degrees. We first analyze the routing properties of the hexagonal array. Then, we propose a triangular tile model and a chord-based internal node division method that can handle both pre-assignment and free-assignment nets without wire crossing. Finally, we develop a novel dynamic programming-based bend minimization method to reduce the number of routing bends in the final solution. Experimental results show that our algorithm can achieve 100% routability with minimized total wirelength and the number of routing bends effectively.

Y-architecture-based flip-chip routing with dynamic programming-based bend minimization

In advanced packages, redistribution layers (RDLs) are extra metal layers for high interconnections among the chips and printed circuit board (PCB). To better utilize the routing resources of RDLs, published works adopted flexible vias such that they can place the vias everywhere. Furthermore, some regions may be blocked for signal integrity protection or manually prerouted nets (such as power/ground nets or feeding lines of antennas) to achieve higher performance. These blocked regions will be treated as obstacles in the routing process. Since the positions of pads, obstacles, and vias can be arbitrary, the structures of RDLs become irregular. The obstacles and irregular structures substantially increase the difficulty of the routing process. This paper proposes a three-stage algorithm: First, the layout is partitioned by a method based on constrained Delaunay triangulation (CDT). Then we present a global routing graph model and generate routing guides for unified-assignment netlists. Finally, a novel tile routing method is developed to obtain detailed routes. Experiment results demonstrate the robustness and effectiveness of our proposed algorithm.

https://dl.acm.org/doi/pdf/10.1145/3508352.3549419

Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures*

Demand for quartz substrate-based aerospace applications in the Q/V and 220 GHz bands is gradually growing. Due to the characteristics of the quartz substrate itself and the excellent surface roughness, it leads to poor adhesion of the metal film on the quartz substrate, and reliability problems, such as metal layer peeling off, often occur in the assembly process. The conventional method to solve this problem is to increase the surface roughness of the quartz substrate, however, this paper proposed to coat a thin polyimide film layer on the surface of the quartz substrate to improve the adhesion. After the coating, the Nickel-Chromium (NiCr), Nickel (Ni) and gold (Au) layer was deposited by sputtering on its surface and the circuit patterns were realized by litho-photography. The fabricated samples were analyzed by appearance inspection firstly. The gold wire pull-test and gold ribbon pull-test were also performed to verify the validation of the process. To assess the effect of polyimide on microwave circuit performance, transmission lines of different lengths have been designed, manufactured and measured. Finally, the samples were subjected to reliability tests such as high temperature storage and temperature cycles to verify the reliability of the coated polyimide layer. 

Study of metalization on polyimide-coated quartz glass for spatial application

The integrated fan-out (InFO) wafer-level chip-scale package is introduced for modern system-in-package designs with larger I/O counts and higher interconnection density. A redistribution layer (RDL) in an InFO package is an extra metal layer for inter-chip connections. To achieve flexible and compact inter-chip connections, the RDL routing problem for InFO packages has become a crucial problem for modern electronic designs. In advanced high-density InFO packages, multiple RDLs with flexible vias are often adopted. On the other hand, to integrate chips of different technology nodes into one package, irregular pad structures need to be considered. To our best knowledge, however, there is no published work for RDL routing considering flexible vias or irregular pad structures. In this paper, we present the first work to handle the routing problem with pre-assigned pad pairs (i.e., the hardest pre-assignment routing problem) on the via-based multi-chip multi-layer InFO package with irregular pad structures. We first propose a layer assignment method based on a weighted maximum planar subset of chords algorithm to concurrently route as many inter-chip nets as possible. We then propose an octagonal tile model with a layout partitioning method to tackle increasingly popular irregular structures. Finally, we develop an efficient linear-programming-based layout optimization algorithm to find solutions with high-quality wirelength and via arrangements. Experimental results demonstrate the effectiveness and robustness of our algorithm.

Yang Hsu

Papers

Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures

Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias