Showing papers by "Yasuhiro Sugimoto published in 2009"
02 Oct 2009
TL;DR: By modifying gain coefficients in the feedback and the input paths, the bias voltage of digital-to-analog converter (DAC) can be set to 1 V and 0 V and MOS switches become easily activated and the 1-V operation of a passive sigma-delta modulator has been realized.
Abstract: The 1-V operation of a passive sigma-delta modulator has been realized. The dc voltage in the signal paths in the second-order switched capacitor filter section was set at 0.2 V so that metal-oxide-semiconductor (MOS) switches in the signal paths would have enough gate-to-source voltage to turn on without using a voltage boosting scheme. The input switch was replaced by a passive resistor to avoid floating. By modifying gain coefficients in the feedback and the input paths, the bias voltage of digital-to-analog converter (DAC) can be set to 1 V and 0 V and MOS switches become easily activated. Moreover, the correlated double sampling (CDS) scheme was adopted to suppress the 1/f noise and offset voltage produced at the input of a comparator. Successful operation from 1-V supply voltage was confirmed by circuit simulation using the 0.18-um complementary MOS (CMOS) process.
11 citations
10 Nov 2009
TL;DR: It is verified that a quadratic slope was the best-fit compensation slope for the current feedback loop of a current-mode DC-DC converter by considering the stability of the inductor current when the current disturbance was applied.
Abstract: In this study, we verified that a quadratic slope was the best-fit compensation slope for the current feedback loop of a current-mode DC-DC converter by considering the stability of the inductor current when the current disturbance was applied. We also verified that the introduction of the input voltage dependency to the quadratic slope enabled the frequency characteristics of the current feedback loop to remain completely constant without depending on the input and output voltage change of a DC-DC converter. The test chip of a MOS current-mode buck DC-DC converter using a 0.35-µm CMOS process and a 5-MHz clock realized two loop frequency bandwidths of 130 kHz and 240 kHz and was operated in two different input and output voltage settings for each frequency bandwidth. As a result, the unaltered gain and phase frequency characteristics were obtained for two different settings in each frequency bandwidth.
5 citations
22 Dec 2009
TL;DR: In this article, a fast response time of less than 10 us has been realized for the sudden output current change between 220 mA and 20 mA of a MOS current-mode buck DC-DC converter which utilizes a quadratic and input-voltage-dependent compensation slope.
Abstract: In this study, a fast response time of less than 10 us has been realized for the sudden output current change between 220 mA and 20 mA of a MOS current-mode buck DC-DC converter which utilizes a quadratic and input-voltage-dependent compensation slope. By using a quadratic and input-voltage-dependent compensation slope, the frequency characteristics of the current feedback loop become constant, and the converter's overall frequency characteristics come to be determined by just adjusting the frequency characteristics in the voltage feedback loop. By changing the time constant in an error amplifier to manipulate the phase margin, the converter's output voltage change becomes small and its response time becomes fast. The test chip of a MOS current-mode buck DC-DC converter using a 0.35-um CMOS process and a 5 MHz clock realized a 40.8 mV output voltage change and a 7.2 us of the response time.
5 citations
19 Jan 2009
TL;DR: A quadratic slope compensation scheme for a current-mode DC-DC converter to obtain stable frequency characteristics without depending on the input and output voltages is proposed.
Abstract: A quadratic slope compensation scheme for a current-mode DC-DC converter to obtain stable frequency characteristics without depending on the input and output voltages is proposed. A 5 MHz and 500 mA buck DC-DC converter with input voltages ranging from 3.3 V to 2.5 V and with output voltages ranging from 2.5 V to 0.5 V was fabricated by using a 0.35 μm CMOS process to verify the effectiveness of the scheme. Little variation of frequency characteristics at frequencies above 200 KHz for the various input and output voltages was observed.
4 citations
02 Oct 2009
TL;DR: A 14-bit MOS DAC is described that has current sources that are free from the non-linear current mismatch caused by ground-line voltage drop and output circuits that do not suffer from time-constant change at the output terminal when the input digital code changes.
Abstract: A 14-bit MOS DAC is described that has current sources that are free from the non-linear current mismatch caused by ground-line voltage drop and output circuits that do not suffer from time-constant change at the output terminal when the input digital code changes. Base current sources are locally classified into two groups with two different values, and the unit current source is constructed by adding one base current source from one group and another base current source from the other group. Eight buffer amplifiers are distributed between the output terminal and current switches to stabilize the voltage at the node where several outputs of unit current sources are tied together and to eliminate the influence of stray capacitances associated with unit current sources and current switches. A 14-bit, 3.3-V DAC was fabricated using 0.35-um CMOS devices. The results show that the DNL and INL are from +0.7 to −0.75 LSB and +1.5 to −1 dB, respectively, and that the SFDR for 2.5-MHz and 10-MHz reconstructed signal waveforms were 77 dB and 67 dB, respectively, with a 50-MHz clock. The current consumption was 25 mA.
1 citations