Bio: Yasushiro Nishioka is an academic researcher from Nihon University. The author has contributed to research in topics: Oxide & Silicon. The author has an hindex of 31, co-authored 239 publications receiving 3435 citations. Previous affiliations of Yasushiro Nishioka include University of Tokyo & Hitachi.
Papers published on a yearly basis
TL;DR: In this article, three kinds of capacitors are proposed: poly-Si/SiO/sub 2/2/ thicknesses of 5, 4, and 3 nm for low-power DRAMs beyond 4 Mb.
Abstract: To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO/sub 2//Ta/sub 2/O/sub 5//SiO/sub 2//poly-Si or poly-Si/Si/sub 3/N/sub 4//Ta/sub 2/O/sub 5//SiO/sub 2//poly-Si (SIS), (b) W/Ta/sub 2/O/sub 5//SiO/sub 2//poly-Si (MIS), and (c) W/Ta/sub 2/O/sub 5/W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO/sub 2/ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950 degrees C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950 degrees C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta/sub 2/O/sub 5/ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5- mu m*3.6- mu m stacked-capacitor DRAM cells. >
•11 Jun 1996
TL;DR: In this article, an improved method of forming a capacitor electrode for a microelectronic structure such as a dynamic read only memory is disclosed which has a high dielectric constant (HDC) material as a capacitance.
Abstract: An improved method of forming a capacitor electrode for a microelectronic structure such as a dynamic read only memory is disclosed which has a high dielectric constant (HDC) material as a capacitor dielectric. According to an embodiment of the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material.
•01 Aug 1994
TL;DR: In this article, a microelectronic structure consisting of a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (i.e., BST 44), is presented, with the sidewall spacer causing the top surface to have a rounded corner.
Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to form a top surface with rounded corners on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO 2 40) and a top surface, with the sidewall spacer causing the top surface to have a rounded corner. The rounded corner of the top surface minimizes crack formation in the high-dielectric-constant material layer.
TL;DR: In this paper, the role of fluorine in relieving the oxide strain near the SiO2/Si interface and in post-irradiation defect-reaction chemistry is discussed.
Abstract: By introducing small amounts of fluorine into the gate oxide, we have been able to significantly alter the radiation response of Metal/SiO2/Si (MOS) capacitors, and their subsequent time dependent behavior. Experimentally we have observed that compared with their control capacitors, which have no fluorine introduced into the oxide, the fluorinated samples exhibit the following major differences: (1) the densities of radiation-induced oxide charge and interface traps are drastically reduced, (2) the gate-size dependence of the radiation-induced interface traps is greatly suppressed, and (3) the overall density of the radiation-induced interface traps continues to decrease with time for many hours after irradiation before a turn-around trend is observed. Possible mechanisms involving the roles that fluorine may play in relieving the oxide strain near the SiO2/Si interface and in the post-irradiation defect-reaction chemistry are discussed.
TL;DR: In this paper, the effects of F and Cl incorporated in SiO/sub 2/ on the susceptibility of the metal/SiO/Sub 2/ (MOS) interface to hot-electron damage have been studied.
Abstract: The effects of F and Cl incorporated in SiO/sub 2/ on the susceptibility of the metal/SiO/sub 2/ (MOS) interface to hot-electron damage have been studied It has been found that, by introducing a very small amount of F or Cl in the thermal SiO/sub 2/, the generation of interface traps by Fowler-Nordheim tunneled hot electrons can be greatly suppressed In addition, the gate-size dependence of hot-electron-induced interface traps, which is normally observed in samples made of dry oxides, does not appear in such chlorinated or fluorinated samples When excess amounts of F or Cl are introduced into SiO/sub 2/, however, the benefits mentioned will diminish The possible roles that F and Cl play that lead to the experimental observations are discussed >
TL;DR: In this paper, a review of the literature in the area of alternate gate dielectrics is given, based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success.
Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...
TL;DR: In this article, the structural phases and the growth of self-assembled monolayers (SAMs) are reviewed from a surface science perspective, with emphasis on simple model systems, and a summary of the techniques used for the study of SAMs is given.
Abstract: The structural phases and the growth of self-assembled monolayers (SAMs) are reviewed from a surface science perspective, with emphasis on simple model systems. The concept of self-assembly is explained, and diAerent self-assembling materials are briefly discussed. A summary of the techniques used for the study of SAMs is given. DiAerent general scenarios for structures obtained by self-assembly are described. Thiols on Au(1 1 1) surfaces are used as an archetypal system to investigate in detail the structural phase diagram as a function of temperature and coverage, the specific structural features on a molecular level, and the eAect of changes of the molecular backbone and the end group on the structure of the SAM. Temperature eAects including phase transitions are discussed. Concepts for the preparation of more complex structures such as multi-component SAMs, laterally structured SAMs, and heterostructures, also with inorganic materials, are outlined. The growth and ways to control it are discussed in detail. Solution and gas phase deposition and the impact of various parameters such as temperature, concentration (in solution) or partial pressure (in the gas phase) are described. The kinetics and the energetics of self-assembly are analyzed. Several more complex issues of the film formation process including non-equilibrium issues are discussed. Some general conclusions are drawn concerning the impact of various molecular features on the growth behavior and concerning the relationship between growth and structural phase diagram. Finally, the potential of self-assembly as a route for the preparation of monolayers with pre-designed properties and SAMs as building blocks in heterostructures as well as application strategies are discussed. ” 2000 Elsevier Science Ltd. All rights reserved.
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
01 May 1989
TL;DR: The historical development and current state of the art in this rapidly expanding field of research is summarized, which has become one of the key exploration areas of modern heterocyclic chemistry.
Abstract: Two-dimensionally extended, polycyclic heteroaromatic molecules (heterocyclic nanographenes) are a highly versatile class of organic materials, applicable as functional chromophores and organic semiconductors. In this Review, we discuss the rich chemistry of large heteroaromatics, focusing on their synthesis, electronic properties, and applications in materials science. This Review summarizes the historical development and current state of the art in this rapidly expanding field of research, which has become one of the key exploration areas of modern heterocyclic chemistry.