Cognitive radio (CR) is the enabling technology for supporting dynamic spectrum access: the policy that addresses the spectrum scarcity problem that is encountered in many countries. Thus, CR is widely regarded as one of the most promising technologies for future wireless communications. To make radios and wireless networks truly cognitive, however, is by no means a simple task, and it requires collaborative effort from various research communities, including communications theory, networking engineering, signal processing, game theory, software-hardware joint design, and reconfigurable antenna and radio-frequency design. In this paper, we provide a systematic overview on CR networking and communications by looking at the key functions of the physical (PHY), medium access control (MAC), and network layers involved in a CR design and how these layers are crossly related. In particular, for the PHY layer, we will address signal processing techniques for spectrum sensing, cooperative spectrum sensing, and transceiver design for cognitive spectrum access. For the MAC layer, we review sensing scheduling schemes, sensing-access tradeoff design, spectrum-aware access MAC, and CR MAC protocols. In the network layer, cognitive radio network (CRN) tomography, spectrum-aware routing, and quality-of-service (QoS) control will be addressed. Emerging CRNs that are actively developed by various standardization committees and spectrum-sharing economics will also be reviewed. Finally, we point out several open questions and challenges that are related to the CRN design.

Cognitive radio networking and communications: an overview

In this paper we propose a novel approach to binocular stereo for fast matching of high-resolution images. Our approach builds a prior on the disparities by forming a triangulation on a set of support points which can be robustly matched, reducing the matching ambiguities of the remaining points. This allows for efficient exploitation of the disparity search space, yielding accurate dense reconstruction without the need for global optimization. Moreover, our method automatically determines the disparity range and can be easily parallelized. We demonstrate the effectiveness of our approach on the large-scale Middlebury benchmark, and show that state-of-the-art performance can be achieved with significant speedups. Computing the left and right disparity maps for a one Megapixel image pair takes about one second on a single CPU core.

Efficient large-scale stereo matching

A significant amount of research in the field of stereo vision has been published in the past decade. Considerable progress has been made in improving accuracy of results as well as achieving real-time performance in obtaining those results. This work provides a comprehensive review of stereo vision algorithms with specific emphasis on real-time performance to identify those suitable for resource-limited systems. An attempt has been made to compile and present accuracy and runtime performance data for all stereo vision algorithms developed in the past decade. Algorithms are grouped into three categories: (1) those that have published results of real-time or near real-time performance on standard processors, (2) those that have real-time performance on specialized hardware (i.e. GPU, FPGA, DSP, ASIC), and (3) those that have not been shown to obtain near real-time performance. This review is intended to aid those seeking algorithms suitable for real-time implementation on resource-limited systems, and to encourage further research and development of the same by providing a snapshot of the status quo.

Review of stereo vision algorithms and their suitability for resource-limited systems

In this paper, we consider the problem of stereo matching using loopy belief propagation. Unlike previous methods which focus on the original spatial resolution, we hierarchically reduce the disparity search range. By fixing the number of disparity levels on the original resolution, our method solves the message updating problem in a time linear in the number of pixels contained in the image and requires only constant memory space. Specifically, for a 800 × 600 image with 300 disparities, our message updating method is about 30× faster (1.5 second) than standard method, and requires only about 0.6% memory (9 MB). Also, our algorithm lends itself to a parallel implementation. Our GPU implementation (NVIDIA Geforce 8800GTX) is about 10× faster than our CPU implementation. Given the trend toward higher-resolution images, stereo matching using belief propagation with large number of disparity levels as efficient as the small ones makes our method future-proof. In addition to the computational and memory advantages, our method is straightforward to implement1.

A constant-space belief propagation algorithm for stereo matching

This paper presents a literature survey on existing disparity map algorithms. It focuses on four main stages of processing as proposed by Scharstein and Szeliski in a taxonomy and evaluation of dense two-frame stereo correspondence algorithms performed in 2002. To assist future researchers in developing their own stereo matching algorithms, a summary of the existing algorithms developed for every stage of processing is also provided. The survey also notes the implementation of previous software-based and hardware-based algorithms. Generally, the main processing module for a software-based implementation uses only a central processing unit. By contrast, a hardware-based implementation requires one or more additional processors for its processing module, such as graphical processing unit or a field programmable gate array. This literature survey also presents a method of qualitative measurement that is widely used by researchers in the area of stereo vision disparity mappings.

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Literature Survey on Stereo Vision Disparity Map Algorithms

Loopy belief propagation (BP) is an effective solution for assigning labels to the nodes of a graphical model such as the Markov random field (MRF), but it requires high memory, bandwidth, and computational costs. Furthermore, the iterative, pixel-wise, and sequential operations of BP make it difficult to parallelize the computation. In this paper, we propose two techniques to address these issues. The first technique is a new message passing scheme named tile-based BP that reduces the memory and bandwidth to a fraction of the ordinary BP algorithms without performance degradation by splitting the MRF into many tiles and only storing the messages across the neighboring tiles. The tile-wise processing also enables data reuse and pipeline, resulting in efficient hardware implementation. The second technique is an O(L) fast message construction algorithm that exploits the properties of robust functions for parallelization. We apply these two techniques to a very large-scale integration circuit for stereo matching that generates high-resolution disparity maps in near real-time. We also implement the proposed schemes on graphics processing unit (GPU) which is four-time faster than standard BP on GPU.

Hardware-Efficient Belief Propagation

In accordance with at least some embodiments of the present disclosure, a processor for performing stereo matching of a first image and a second image is described. The processor may include a first pipeline stage configured to generate data costs associated with a first tile selected from the first image, wherein the data costs is generated based on pixels in the first tile and corresponding pixels in the second image. The processor may include a second pipeline stage configured to generate disparity values associated with the first tile and an outbound message from the first tile to one of neighboring tiles in the first image, wherein the disparity values and the outbound message are generated based on the data costs and inbound messages from the neighboring tiles to the first tile. The processor may further include a third pipeline stage configured to store the disparity values and the outbound message in a memory, wherein the outbound message is used by the second pipeline stage as one of the inbound messages during processing of a second tile selected from the first image.

Stereo-Matching Processor Using Belief Propagation

A method of revising depth of a three-dimensional (3D) image is disclosed. The method comprises the following steps: firstly, at least one initial depth map associated with one image of the 3D image pair based on stereo matching technique is received, wherein the one image comprises a plurality of pixels, and the initial depth map carries an initial depth value of each pixel. Then, the inconsistence among the pixels of the one image of the 3D image pair is detected to estimate a reliable map. Finally, the initial depth value is interpolated according to the reliable map and the proximate pixels, so as to generate a revised depth map by revising the initial depth value.

System and method of revising depth of a 3d image pair

A nonlinear depth remapping method includes the following steps: firstly, an initial depth map associated with at least one image is received, with the image comprising a plurality of pixels and the initial depth map carrying an initial depth value of each pixel. Then, an exponential function is utilized to adjust the initial depth values, so as to generate an adjusted depth map.

Nonlinear depth remapping system and method thereof

A 4 K $\,\times\,$ 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.49 $\,\times\,$ 1.45 mm $^{2}$ die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content features leading to over 68.5% and 83% of complexity reduction in intra and inter coding, respectively. A fully parallel processing element (PE) array is adopted in SAO and IP/ME, which reduce number of accesses to SRAM by 48.7% and 78.4%, respectively. A shared memory management unit (MMU) including line-store SRAM pool (LSSP) and data bus translation (DBT) techniques efficiently reuses and packs the neighboring pixels which contribute 71.6% of external bandwidth reduction. This chip achieves 4096 $\,\times\,$ 2160@30 fps HEVC encoding/decoding and consumes 126.73 mW, 0.5 nJ/pixel of energy efficiency, under 494 MHz and 350 MHz of clock frequency, enabling 4 K video services for smart-phone applications.

Yen-Chieh Lai

Papers

Hardware-Efficient Belief Propagation

Stereo-Matching Processor Using Belief Propagation

System and method of revising depth of a 3d image pair

Nonlinear depth remapping system and method thereof

A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications