An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A method for forming a write pole comprises forming a stop layer over a substrate layer of a wafer, the stop layer having an opening above a damascene trench in the substrate layer, and forming a buffer layer over the stop layer, the buffer layer having an opening above the opening of the stop layer. The method further comprises plating a layer of magnetic material over the wafer, disposing a first sacrificial material over a region of the magnetic material above the damascene trench, performing a milling or etching operation over the wafer to remove the magnetic material not covered by the first sacrificial material and to remove the first sacrificial material, disposing a second sacrificial material over the wafer, and performing a polishing operation over the wafer to remove the region of the magnetic material above the damascene trench, the second sacrificial material, and the buffer layer.

Damascene write poles produced via full film plating

A method for manufacturing a perpendicular magnetic recording transducer is described. A metallic underlayer, an insulator on the metallic underlayer, and a metal mask on the insulator are provided. The metal mask has an aperture therein. A trench is formed in the insulator. The trench's bottom is narrower than its top and includes part of the metallic underlayer. The top has a width of not more than 0.28 micron. A nonmagnetic seed layer that substantially covers at least the trench bottom and sides and that has a thickness of at least five hundred Angstroms is provided. A perpendicular magnetic pole material is plated on at least part of the seed layer. A CMP is performed, removing part of the perpendicular magnetic pole material. A remaining portion of the perpendicular magnetic pole material forms a perpendicular magnetic recording pole. The nonmagnetic seed layer is a stop layer for the CMP.

Method for manufacturing a perpendicular magnetic recording transducers

A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.

Dual damascene process using metal hard mask

The present invention relates to a method of fabricating a flash memory device. In a method according to an aspect of the present invention, a first hard mask film is formed over a semiconductor laminate. A plurality of first hard mask patterns are formed by etching an insulating layer for a hard mask. Spacers are formed on top surfaces and sidewalls of the plurality of first hard mask patterns. A second hard mask film is formed over a total surface including the spacers. Second hard mask patterns are formed in spaces between the spacers by performing an etch process so that a top surface of the spacers is exposed. The spacers are removed. Accordingly, gate patterns can be formed by employing hard mask patterns having a pitch of exposure equipment resolutions or less.

Method of fabricating flash memory device

A dual damascene process involves forming a first passivation layer, a first dielectric layer and a second passivation layer on a substrate of a semiconductor wafer. A first lithography and etching process is performed to form at least one via hole in the second passivation layer and the first dielectric layer. Thereafter, a second dielectric layer and a third passivation layer are formed on the surface of the semiconductor wafer followed by performing a second lithography and etching process to form at least one trench in the third passivation layer and the second dielectric layer. The trench and the via hole together construct a dual damascene structure. Finally, a barrier layer and a metal layer are formed on the surface of the semiconductor wafer, and a chemical-mechanical-polishing (CMP) process is performed to complete the dual damascene process.

Dual damascene process

A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. Each of the multiple exposures is provided with a respective illuminating setting that is optimized for one duty ratio of the photomask. Thereby, an optimum through-pitch performance for pattern transfer from the photomask unto the photoresist is obtained. Then, a development is performed on the photoresist.

Photolithography process with multiple exposures

An extended 248nm lithography process with alternating phase-shift masks (PSMs) and etch-trimming techniques has produced 50nm gate critical dimensions (CDs). Well-controlled CD uniformity and line-end edge roughness (LER) are also demonstrated in this work. The primary factor in the improvement of through-pitch proximity bias was phase shifter width. With optimum shifter width, where pitches are greater than 600 nm, a through-pitch proximity bias of less than 10 nm can be obtained. Photoresist also has a significant role in implementing alternating PSMs, requiring high activation energy and suitable thickness. Soft-bake and post-bake temperatures were determined to enlarge the depth-of-focus (DOF). The forbidden pitch effect was enhanced to constrain the common process window after optical proximity correction (OPC) had been implemented. However, proximity bias can be kept constant with changeable diffusion length due to the through-pitch CD profiles, all isolated like. Improvement of through-focus CD at the forbidden pitch was examined by optimizing diffusion length; the common process window can be improved by 25%. All process results, including line-end roughness, DOF, exposure latitude, well-controlled CD uniformity, and through-pitch proximity bias, showed that 248 nm photolithography with alternating phase shifting mask could meet the requirements of 100nm node application.

Yeong-Song Yen

Papers

Dual damascene process

Photolithography process with multiple exposures

Challenges of 50-nm gate process in alternating phase shifting lithography