Line-impedance matching and signal conditioning capabilities for high-speed feed-forward voltage-mode transmit drivers

This work introduces high-frequency inter-chip links. This approach is proposed to connect two chiplets on a silicon interposer at high speed; it can be used for either active or passive silicon interposer. This approach is suggested to support the increasing need for higher data rates and larger bandwidths among different components such as CPU/GPU to memory. To limit the distortion of the signal, we use a 60-GHz carrier to transmit in the propagating LC region of the wires. This significantly reduces the signal distortion as compared to base band communications working in the RC region. Furthermore, we used duobinary modulation to achieve higher bandwidth per channel, this modulation having the same spectral efficiency as PAM-4 without the need for extra comparators. Hereafter, we simulated a 7-mm long interposer channel using 3D EM tool, we used 28-nm FD-SOI technology for the chiplets, and BiCMOS 130 nm back-end-of-line for the interposer channel, both technologies being from STMicroelectronics. For a proof-of-concept, simulation results using a transmitter and receiver in 28-nm FD-SOI technology are shown.

7-mm low-latency inter-chiplet serial link with silicon interposer

This paper proposes a novel loss evaluating method considering coupling effects based on a parallel RLC differential transmission line (DTL) model in nanometer CMOS process. Through extracting the coupling parasitical parameters, the decoupling partial differential equations of transmission lines are established, thus a loss evaluating expression is proposed. The analytical method enables the estimation of the loss within 6.48% average error compared with measured results in 180nm CMOS process and 5.20% average error compared with HFSS simulation in 65nm CMOS process.

A novel loss evaluation method for differential transmission lines

2.56 Gbps CMOS CML-transceiver is presented. The key feature of the design is capability of working with specific inductive load and transmitting data to the remote room about 1 meter away from the experimentation vicinity. Some radiation tolerance techniques used are shown. Testing methodology is briefly described, and concepts in test board realization are provided. The transceiver was designed as an interface part of the data concentrator ASIC, intended for the frontend electronics of the time-projection chamber of the MPD experiment at NICA nuclotron.

2.56 Gbps CML transceiver for data concentrator ASIC

Abstract 2.56 Gbps CMOS CML-transceiver is presented. The key feature of the design is capability of working with specific inductive load and transmitting data to the remote room about 1 meter away from the experimentation vicinity. Some radiation tolerance techniques used are shown. Testing methodology is briefly described, and concepts in test board realization are provided. The transceiver was designed as an interface part of the data concentrator ASIC, intended for the frontend electronics of the time-projection chamber of the MPD experiment at NICA nuclotron. 

In order to achieve high-speed and low-power signal transmission in long interconnection of Network on Chip (NoC), the performance of co-planar differential transmission line (DTL) is analyzed by HFSS in this paper Current Mode Logic (CML) transmitter and Continuous-Time Linear Equalizer (CTLE) are adopted to reduce the impact of line loss and inter-symbol interference (ISI) Simulation results by Spectre show that the transceiver can transmit 20Gbps data through 10mm DTL in 130nm standard CMOS process, the unit power is only 044pj/bit

Yi Liu

Papers

A 20Gbps on-chip transceiver with equalization technique for global signal transmission

A novel loss evaluation method for differential transmission lines