A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost. Full Text: PDF

An FPGA Implementation of On Chip UART Testing with BIST Techniques

In parallel communication the cost as well as complexity of the system increases due to simultaneous transmission of data bits on multiple wires. Serial communication alleviates this drawback and emerges as effective candidate in many applications for long distance communication as it reduces the signal distortion because of its simple structure. This paper focuses on the VHDL implementation of UART with status register which supports asynchronous serial communication. The paper presents the architecture of UART which indicates, during reception of data, parity error, framing error, overrun error and break error using status register. The whole design is functionally verified using Xilinx ISE Simulator.

VHDL Implementation of UART with Status Register

Universal Asynchronous Receiver Transmitter (UART) is widely used in data communication process especially for its advantages of high reliability, long distance and low cost In this paper, we present the design of 9-bit UART modules based on Verilog HDL This design features automatic address identification in the character itself We have implemented the VLSI design of the module and pass data between the proposed 9-bit UART module with a host CPU The design consists of receiver module, transmitter module, prescaler module and asynchronous FIFOs We have explained the functions of each individual sub-modules and how the design works in simulation

Design of a 9-bit UART module based on Verilog HDL

This paper details the design and implementation of SoC's UART-SPI Interface The UART-SPI interface provides usage for the universal asynchronous receiver/transmitter (UART) to serial peripheral interface (SPI) This interface can be used to communicate to SPI slave devices from a PC with UART port The interface consists of three blocks: the UART interface, the UART-to-SPI interfacing block and the SPI Master interface

Optimal implementation of UART-SPI Interface in SoC

With the rapid growth of Integrated Circuits (ICs) technology, the complexity of the circuits has also increased. As a result, the complexity of the circuit demands self-testability in hardware to mitigate the product failure. Built-in-self-test (BIST) is such a technique which can meet the demand of self-testability with an effective solution over costly circuit testing system. This paper represents designing and implementation of a Universal Asynchronous Receiver Transmitter (UART) with self-testing ability. In order to attain compact, stable and reliable data transmission, the UART is designed with Verilog HDL language and synthesized on Spartan2 FPGA. Here, the Baud Rate of the UART is 4 Mbps. This UART also utilizes the RS-422 standard.

Design and implementation of a BIST embedded high speed RS-422 utilized UART over FPGA

UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language can be integrated into the FPGA to achieve compact, stable and reliable data transmission. It's significant for the design of SOC. The simulation results with Quartus II are completely consistent with the UART protocol.

Yi-yuan Fang

Papers

Design and Simulation of UART Serial Communication Module Based on VHDL