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Showing papers by "Yihwan Kim published in 2004"


Patent
21 Sep 2004
TL;DR: In this paper, a method for depositing a silicon film or silicon germanium film on a substrate is provided, which includes placing the substrate within a process chamber and heating the substrate surface to a temperature in the range from about 600 C to about 900 C while maintaining a pressure in the process chamber in the ranges from about 13 Pa (0.1 Torr) to about 27 kPa (200 Torr).
Abstract: In one embodiment a method for depositing a silicon film or silicon germanium film on a substrate is provided which includes placing the substrate within a process chamber and heating the substrate surface to a temperature in the range from about 600 C to about 900 C while maintaining a pressure in the process chamber in the range from about 13 Pa (0.1 Torr) to about 27 kPa (200 Torr). A deposition gas is provided to the process chamber and includes SiH4, an optional germanium source gas, an etchant, a carrier gas and optionally at least one dopant gas. The silicon film or the silicon germanium film is selectively and epitaxially grown on the substrate. One embodiment includes a method for depositing a silicon-containing film with an inert gas as the carrier gas. Methods also include the fabrication of electronic devices utilizing selective silicon germanium epitaxial films.

113 citations


Proceedings ArticleDOI
15 Jun 2004
TL;DR: In this article, the best reported PMOS transistor at a 37 nm gate length (Lg) built on a process with a recessed SiGe epitaxial layer is discussed.
Abstract: Results from the best reported PMOS transistor at a 37 nm gate length (Lg) built on a process with a recessed SiGe epitaxial layer are discussed The process details include successful integration of SiGe at the drain extension (DE) location A highly compressive SiGe layer, in close proximity to the channel, results in large hole mobility improvements HRTEM based lattice parameter extractions confirm the compressive strain in the channel In situ doped B in SiGe can be activated to a higher degree than implanted B in bulk Si resulting in further improvements from the lower DE resistance Both changes combine to give an unprecedented 35% PMOS performance improvement Process and device simulations that predict the observed parametric behavior quantitatively isolate the improvements to be /spl sim/ 28% from stress and 7% from DE resistance improvement

109 citations


Journal ArticleDOI
15 Mar 2004
TL;DR: In this article, fabrication of epitaxial Si/SiGe/Si-type optical waveguides with a well-controlled refractive index difference between the core and the cladding and with low transmission losses was reported.
Abstract: This paper reports fabrication of epitaxial Si/SiGe/Si-type optical waveguides with a well-controlled refractive index difference between the core and the cladding and with low transmission losses. A SiGe strip with a cross-section in the range of 0.5 μm ×0.5 μm– 5 μm ×5 μm was formed on the Si substrate. Then, a Si upper cladding layer was deposited. Some samples incorporated a compositionally graded layer between the SiGe core and the Si cladding layer. The fabricated structures show that the index contrast, Δn, increases linearly with the increasing Ge atomic concentration x in the Si1−xGex cores (Δn=αx, where α=1 at a wavelength of 0.633 μm). We determined waveguide transmission losses by measuring the ratio between the input and output optical power values through straight waveguides of different lengths. For waveguides with an index contrast (Δn/n) of 0.6% between the Si0.98Ge0.02 core and the Si cladding, the loss value for the wavelength at 1.55 μm was approximately 0.31 dB/cm. Structures with a graded layer show higher loss values than those without, which may be attributed to the asymmetric Ge grading in the horizontal and vertical directions. No measurable polarization dependence of the losses has been detected in waveguides, in agreement with the results of X-ray diffractometry that has shown relaxation of the Si0.98Ge0.02 on Si.

3 citations