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Showing papers by "Yihwan Kim published in 2010"


Proceedings ArticleDOI
01 Dec 2010
TL;DR: In this article, high performance Ge nMOSFET is fabricated using laser annealing of ion-implanted antimony (Sb) dopants which provides donor activation beyond 1×1020cm−3 in germanium.
Abstract: For the first time, high performance Ge nMOSFET is fabricated using laser annealing of ion-implanted antimony (Sb) dopants which provides donor activation beyond 1×1020cm−3 in germanium. Record I on /I off > 105 is demonstrated for n+/p junctions combined with significant reduction of contact resistance to 7×10−7 Ω-cm2. Performance projections for ITRS HP 22nm technology node are also discussed.

42 citations


Patent
03 Aug 2010
TL;DR: In this paper, a method for selectively depositing an epitaxial layer on a substrate having a monocrystalline first surface and a non-monocrystaline second surface is presented.
Abstract: Methods for selectively depositing an epitaxial layer are provided herein. In some embodiments, providing a substrate having a monocrystalline first surface and a non-monocrystalline second surface; exposing the substrate to a deposition gas to deposit a layer on the first and second surfaces, the layer comprising a first portion deposited on the first surfaces and a second portion deposited on the second surfaces; and exposing the substrate to an etching gas comprising a first gas comprising hydrogen and a halogen and a second gas comprising at least one of a Group III, IV, or V element to selectively etch the first portion of the layer at a slower rate than the second portion of the layer. In some embodiments, the etching gas comprises hydrogen chloride (HCl) and germane (GeH4).

25 citations


Proceedings ArticleDOI
21 Jun 2010
TL;DR: In this paper, the first ultra shallow junctions (x j 1×1020 cm−3) were achieved for all dopant atoms (P/As/Sb/B) using laser thermal processing.
Abstract: For the first time, ultra shallow junctions (x j 1×1020 cm−3) is achieved for all dopant atoms (P/As/Sb/B) using Laser Thermal Processing. We also show ultrathin (0.6nm), high quality GeO 2 interfacial layer for gate dielectric, which provides substrate orientation independent D it and mobility enhancement for Ge high-k N/P MOSFETs.

2 citations