An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Lasing is experimentally demonstrated in a direct bandgap GeSn alloy, grown directly onto Si(001). The authors observe a clear lasing threshold as well as linewidth narrowing at low temperatures.

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Lasing in direct-bandgap GeSn alloy grown on Si

Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.

Semiconductor Devices and Methods of Manufacture Thereof

Embodiments of the invention provide processes to deposit silicon-containing materials, such as selectively depositing an epitaxial silicon-germanium material containing a high dopant concentration. In one example, a substrate is exposed to at least two different process gases to deposit one layer on top of another layer. One process gas contains dichlorosilane, a germanium source and an etchant while the next process gas contains silane and an etchant. In other examples, a process gas contains dichlorosilane, methylsilane and hydrogen chloride or silane, methylsilane and hydrogen chloride. In one aspect, a deposited layer has interstitial sites within a crystalline lattice and contains about 3 at% or less of carbon within the interstitial sites and is subsequently annealed to incorporate carbon within substitutional sites of the crystalline lattice. In another aspect, a silicon-germanium stack has first, second and third layers containing germanium concentrations of about 25 at% or less, about 25 at% or more and about 5 at% or less.

Methods to fabricate MOSFET devices using a selective deposition process

Methods for formation of epitaxial layers containing n-doped silicon are disclosed, including methods for the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. Formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source at a first temperature and pressure and then exposing the substrate to an etchant at a second higher temperature and a higher pressure than during deposition.

Selective Formation of Silicon Carbon Epitaxial Layer

Methods for formation of epitaxial layers containing n-doped silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source. An epitaxial layer may have considerable tensile stress which may be created in a significant amount by a high concentration of n-dopant. A layer having n-dopant may also have substitutional carbon. Phosphorus as an n-dopant with a high concentration is provided. A substrate having an epitaxial layer with a high level of n-dopant is also disclosed.

Phosphorus containing si epitaxial layers in n-type source/drain junctions

In one embodiment a method for depositing a silicon film or silicon germanium film on a substrate is provided which includes placing the substrate within a process chamber and heating the substrate surface to a temperature in the range from about 600 C to about 900 C while maintaining a pressure in the process chamber in the range from about 13 Pa (0.1 Torr) to about 27 kPa (200 Torr). A deposition gas is provided to the process chamber and includes SiH4, an optional germanium source gas, an etchant, a carrier gas and optionally at least one dopant gas. The silicon film or the silicon germanium film is selectively and epitaxially grown on the substrate. One embodiment includes a method for depositing a silicon-containing film with an inert gas as the carrier gas. Methods also include the fabrication of electronic devices utilizing selective silicon germanium epitaxial films.

METHODS OF SELECTIVE DEPOSITION OF HEAVILY DOPED EPITAXIAL SiGe

In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amorphous surface and/or a polycrystalline surface. The substrate is exposed to a deposition gas to deposit an epitaxial layer on the monocrystalline surface and a polycrystalline layer on the second surface. The deposition gas preferably contains a silicon source and at least a second elemental source, such as a germanium source, a carbon source and/or combinations thereof. Thereafter, the method further provides exposing the substrate to an etchant gas to etch the polycrystalline layer and the epitaxial layer in a manner such that the polycrystalline layer is etched at a faster rate than the epitaxial layer. The method may further include a deposition cycle that includes repeating the exposure of the substrate to the deposition and etchant gases to form a silicon-containing material with a predetermined thickness.

Yihwan Kim

Papers

Methods to fabricate MOSFET devices using a selective deposition process

Selective Formation of Silicon Carbon Epitaxial Layer

Phosphorus containing si epitaxial layers in n-type source/drain junctions

METHODS OF SELECTIVE DEPOSITION OF HEAVILY DOPED EPITAXIAL SiGe

Selective epitaxy process with alternating gas supply