In this paper, we propose and investigate two novel applications of absorbing materials to suppress high-frequency couplings in high-speed interconnects. In the first application, absorbing materials are added to connector housing to reduce the noises caused by crosstalk and resonances. In the second application, a low-emission inductor is proposed by applying absorbing materials surrounding the body of an inductor. Full-wave simulations and measurements are performed to verify the proposed techniques. Results show absorbing materials significantly improve the performance of signal/power integrity and greatly reduce electromagnetic interference for high-speed digital system designs.

Suppression of Couplings in High-Speed Interconnects Using Absorbing Materials

A redriver is provided that includes a receiver to receive a signal from a first device that includes a portion of a defined binary sequence, a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence, the LFSR to generate an expected version of the binary sequence from the seed, and pattern checking logic to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.

Redriver link testing

The invention provides a design method for reducing crosstalk effect of Dual Stripline type wiring and belongs to the field of designs for reducing the crosstalk effect of Dual Stripline type wiring By the design method, staggered parallel type wiring is adopted for long-distance transmission parallel wiring with adjacent signal layers, and center distances, Center-to-Center Spacing=W+S-1mil, of two differential pairs are kept to allow crosstalk noise to be zero, thus noise effect between the adjacent signal layers is reduced, high-speed signal quality is effectively improved, and cost performance of product design is enhanced

Design method for reducing crosstalk effect of Dual Stripline type wiring

Switching voltage regulators are prevalent in electrical systems as power solution. The periodic transition edges of voltage and current in switching voltage regulator generate power noise, which can be coupled to the adjacent high-speed signal lines when the coupling path is effective. This paper introduces a failure case on high-speed signal caused by power noise. By simulation and analysis, it explains the phenomenon of differential mode power noise on differential high-speed signal traces, explores the noise coupling mechanism of signal traces crossing switching voltage regulator area and discusses the mitigations of this power noise coupling issue. The measurement results show proper modifications can effectively reduce the power noise.

Noise coupling analysis for high speed differential trace crossing switching voltage regulator area

A microserver was developed and studied to shrink servers’ physical dimensions and increase the efficiency of the spatial usage of data centers. It was also developed to apply more computing power using a scale‐out feature and lessen the power consumption. To achieve this, the first requirement was to integrate a large number of devices and boards into a chassis. To do so, backplanes were used for the communication within the chassis. To enhance the performance of the servers, high‐speed signals were used in the small area of a printed circuit board (PCB). We developed the proposed server as a microserver. It can integrate 64 servers (CPUs) in a single chassis. A system interconnection network is built into the proposed server to connect with each server using serial RapidIO (SRIO). To increase the density of the proposed server, a system interconnection module connects with eight servers (CPUs) on two computer cards. The detailed configuration of the proposed server is described later. One system interconnection module must support the SRIO Gen 2.1 and PCIe Gen 2 at a maximum of 20 Gbps per port. It must also place and route 160 differential wires with a maximum bandwidth of 800 Gbps. Therefore, the signal integrity that we define as a crosstalk on the module is the most important requirement to achieve good results. Received: 13 March 2018 | Revised: 23 August 2018 | Accepted: 22 January 2019 DOI: 10.4218/etrij.2018-0021

Signal integrity analysis of system interconnection module of high-density server supporting serial RapidIO

Dual-stripline is gaining popularity in computer designs to save printed circuit board (PCB) cost and achieve more compact form factor. A key concern in dual-stripline design is the inter-layer crosstalk (ILC). In this paper, differential dual-stripline crosstalk is investigated, and a complete design strategy is provided. In addition to the conventional crosstalk mitigation techniques, an innovative wiring technique is proposed to reduce ILC for parallel dual-striplines. The proposed routing strategy can effectively mitigate the impact of ILC, and, as a result, enable high-density PCB layout, achieve compact form factor, and save the bill of material (BOM) cost.

Inter-layer crosstalk management in differential dual-striplines

In a server system, the switching voltage regulator (VR) noise coupled to the IO pins of the adjacent memory riser connector through the open air above the base board, and the link performance was impacted by the coupling. A simulation flow was developed to reproduce this EMI phenomenon. The flow first used electromagnetic field solvers to extract the VR related power network and the VR-IO coupling network, and then the di/dt and dv/dt noise sources and the induced IO noise were solved in HSpice®. The simulation revealed the underlying coupling mechanism: The high frequency current loop formed by the power MOSFET, the VR power shapes, the snubber RC circuit at the bottom layer of the board, and the stitching via acted as a transmitting loop antenna, and the radiating field propagated through the air and was picked up by another loop (receiving antenna) formed by the riser connector pins. An effective mitigation method is to use bigger snubber resistor to damp this near field radiation. Both the coupling theory and the effectiveness of the mitigation method were proved by the measurements.

Switching voltage regulator noise coupling to connector signal pins through near field radiation

Noise caused by switching voltage regulator (VR noise) can have a big impact on system signal / power performance, leading to signal integrity (SI) / power integrity (PI) issues. This paper introduces systematic ways of reducing VR noise as well as VR noise analysis methods. And a real design case with VR noise issue is shared with simulation and measurement results.

VR noise analysis and reduction in printed circuit board designs

Due to non-LTI behaviour of re-driver, simulation methodology and model format are still working in progress for continuous improvement on accuracy and efficiency to perform statistical analysis such as BER for high-speed serial IO links. In this paper, a measurement based methodology is proposed and introduced to provide a flow and methodology to evaluate re-driver link performance. The methodology is based on re-driver assessment board to obtain reference channel through measurement by meeting industry IO specifications. Channel Quality Comparison (CQC) is then introduced and used to evaluate risk level of the proposed design topology by benchmarking to the reference channels. Design engineers can use the flow and methodology introduced in this paper to evaluate link performance for their proposed topology in addition to using simulation. A design example on test platform for USB3 is reported to demonstrate the usage with measurement results.

A new design flow to evaluate high-speed SerDes link performance with re-driver

Dual stripline routing is more and more widely used in the modern high speed PCB design due to its cost advantage of reduced overall layer count. However, the major challenge of a successful dual stripline design is to handle the additional interferences introduced by the signals on adjacent layers. This paper studies the crosstalk effect of the dual stripline with both parallel and angled routing, and proposes design solutions to tackle the challenge. Analytical and empirical algorithms are proposed to estimate the crosstalk waveforms from multiple aggressors, which provide quick design risk assessment, and the waveform is well correlated to the 3D full wave EM simulation results.

Yinglei Ren

Papers

Inter-layer crosstalk management in differential dual-striplines

Switching voltage regulator noise coupling to connector signal pins through near field radiation

VR noise analysis and reduction in printed circuit board designs

A new design flow to evaluate high-speed SerDes link performance with re-driver

Crosstalk analysis for dual stripline with parallel and angled routing