: The fabrication of a silicon carbide (SiC) junction field effect transistor (J-FET) was shown practicable. Several amplifier designs were breadboarded with silicon devices to study the required parameters. A simplified building block amplifier was constructed and tested. (Author)

High Temperature Electronics.

A low-dropout (LDO) regulator with a quiescent current in the tens of nanoampere range and operating from 800-mV supply is proposed. A rail-to-rail buffer with zero input–output (I/O) voltage shift and based on the differential flipped voltage follower is used for combined gate and bulk driving of the output device. Therefore, bulk modulation with forward body bias is implemented without any additional amplifier. The proposed buffer is a crucial block for the sub-1-V supply and for limiting the contribution of the output device to the quiescent current. The error amplifier (EA) is adaptively biased with a bias shaper block, which implements a current limiting at high loads and a linear dependence on the output current at moderate loads. The feedback signal for the bias control is the output of the amplifier instead of the gate voltage of the pass device, thus combining a nanoampere bias at light load with the ability to follow a fast output current transient. Finally, a corner-tracking load is used to set the bias current of the output device to the minimum value at the target stability margin over the temperature and process parameters’ space. The LDO was implemented in a 55-nm CMOS technology. The measured quiescent current is 16 nA with a minimum power supply rejection of 42.7 dB up to 50 kHz and a maximum load current of 10 mA. In order to compare the transient behavior of the state-of-the-art designs, a modified figure of merit is proposed, taking into account the penalty caused by the low supply.

A 10-mA LDO With 16-nA IQ and Operating From 800-mV Supply

BIMOS transistor is a useful device and now compliant in advanced CMOS technology. This device acts with high controlled current gain. Thus, it is an efficient candidate for Electrostatic Discharge (ESD) protection. Moreover it is well known that ESD protection for advanced CMOS technologies is a major challenge due to down-scaling which introduces a reduction of the intrinsic robustness. This paper introduces the BIMOS ESD approach with simulations in 45nm. Silicon measurements are performed on 32 nm CMOS high k metal gate.

BIMOS transistor and its applications in ESD protection in advanced CMOS technology

This article proposes a new silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection device suitable for 5-V applications. The proposed ESD protection device has an additional n-p-n parasitic bipolar transistor that provides an extremely short ESD discharge path. Compared with the conventional Low-Voltage-Trigger SCR (LVTSCR) and Low-Ron SCR (LRSCR), it has excellent ON-resistance and improved reverse characteristics. Furthermore, it has structurally enhanced trigger voltage and holding voltage characteristics. A conventional LVTSCR, LRSCR, and the proposed ESD protection device were fabricated with the same width using a 0.18- $\mu \text{m}$ bipolar CMOS DMOS (BCD) process to verify the improvement in electrical characteristics and current driving capability of the new device. Transmission line pulsing (TLP) and a hot chuck control system were used to measure and compare the latch-up, electrical characteristics, and temperature reliability of the three devices. The measurements demonstrate that the proposed ESD protection device provides improved reliability and higher area efficiency for 5 V or similar applications.

A New SCR Structure With High Holding Voltage and Low ON-Resistance for 5-V Applications

Dual-directional silicon-controlled rectifiers (DDSCRs), which provide both positive and negative electrostatic discharge (ESD) surge paths, are ESD protection devices with an excellent area efficiency. However, DDSCRs have a low holding voltage for use in 5 V-class applications, with a relatively high on-state resistance because of the elongated ESD surge path compared to unidirectional SCRs. In this paper, we propose a novel DDSCR with a higher holding voltage and a better ESD tolerance than conventional low-triggering DDSCRs (LTDDSCRs), realized by operating two additional parasitic bipolar transistors. The proposed ESD protection device was developed through a 0.18- $\mu \text{m}$ CMOS process, and a timeline pulse system was used to verify its properties. The measurement results show that the proposed ESD protection device exhibits an improved tolerance and a high holding voltage and is expected to be reliable in 5 V-class applications

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A New Dual-Direction SCR With High Holding Voltage and Low Dynamic Resistance for 5 V Application

Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology

This paper introduces a novel silicon controlled rectifier (SCR)-based device for ESD power clamp and I/O clamp. The device obtained the high holding voltage and low triggering voltage by adding a p-drift junction and n-well in the cathode region. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection. The proposed device is designed by compatible 0.35um BCD(Bipolar-CMOS-DMOS) technology. We investigated electrical characteristic by measurement and TCAD simulation. In the measurement result, the proposed device has triggering voltage of 12.8V and holding voltage of 10V. The proposed device has high holding voltage as well as high robustness and second breakdown current. (It2=67.4mA/um)

The novel SCR-based ESD protection device with high holding voltage

A Low-area Low Drop-out (LDO) regulator using the body biasing technique is presented. The body biasing technique can decrease the threshold voltage and increase the drain current. The technique is applied to the error amplifier, voltage buffer and pass transistor in the proposed LDO regulator to reduce chip size and provide the proposed LDO regulator with the same performance as the conventional LDO regulator. A pass transistor using the technique can reduce its size by 5.5% at 100mA load condition. The proposed current mirror in the error amplifier and voltage buffer has about 61% smaller area at coterminous performance. The proposed LDO regulator showed about 26% smaller area, not including the bias blocks, while it showed coterminous performance and characteristics.

A design of low-area low drop-out regulator using body bias technique

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate-triggered NMOS and a gate-substrate-triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn-on speed. The proposed ESD protection devices are designed using 0.13 µm CMOS technology. The experimental results show that the proposed substrate-triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn-on time of 37 ns. The proposed gatesubstrate-triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.

https://onlinelibrary.wiley.com/doi/pdf/10.4218/etrij.09.1209.0045

Yong-Seo Koo

Papers

Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology

The novel SCR-based ESD protection device with high holding voltage

A design of low-area low drop-out regulator using body bias technique

Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

Analysis of the electrical characteristics of power LDMOSFETs having different design parameters under various temperature