Showing papers by "Yoshihito Amemiya published in 1993"

A floating-gate analog memory device for neural networks

Abstract: A floating-gate MOSFET device that can be used as a precision analog memory for neural network LSIs is described. This device has two floating gates. One is a charge-injection gate with a Fowler-Nordheim tunnel junction, and the other is a charge-storage gate that operates as a MOSFET floating gate. The gates are connected by high resistance, and the charge-injection gate is small so that its capacitance is much less than that of the charge-storage gate. By applying control pulses to the charge-injection gate, it is possible to charge and discharge the MOSFET floating gate in order to modify the MOSFET current with high resolution over 10 b. The charge injection can be carried out without disturbing the MOSFET output current with high voltage control pulses. This device is useful for on-chip learning in analog neural network LSIs. >

Neural-processing-type optical WDM demultiplexer

Abstract: A neural-processing-type optical WDM demultiplexer consisting of a multimode waveguide, a detector array, and an electrical neural network (NN) is described. This demultiplexer regenerates the original signals by recognizing the different speckle patterns of each channel with the pattern-recognition function of an NN. The demultiplexing properties can be flexibly changed, in the electrical domain, by modifying the parameters of the NN, and only simple optical components are required for implementation. Three 150-Mb/s WDM signals are successfully demultiplexed with a silica-based multimode planar waveguide, a four-channel detector array, and two high-speed analog neural network integrated circuits (ANNIC's), each of which has sixteen modifiable weights and four sigmoidal transfer functions. >

Very-high-speed analog neural network LSI implementation using super self-aligned Si bipolar process technology

Abstract: A very-high-speed ten-neuron analog neural network LSI chip is fabricated for the first time with super self-aligned Si bipolar process technology. The LSI consists of ten neurons and 100 electrically modifiable synaptic weights. The neural network nonlinear mapping function to solve the four-bit parity problem has been successfully demonstrated at 150 megapatterns/sec. The operation speed of this neural network is, to the best of the authors' knowledge, the fastest yet reported.