Yosseff Levanoni

TL;DR: In this article, a hardware assisted transactional memory system with open nested transactions is presented, where a top level transaction can be implemented in software, and thus not be limited by hardware constraints typical when using hardware transactional systems.

TL;DR: Transactional memory compatibility type attributes are associated with intermediate language code to specify, for example, that intermediate code must be run within a transaction, or must not be run in a transaction as mentioned in this paper.

TL;DR: In this paper, the authors propose a method to handle garbage collection and exceptions in hardware assisted transactions. But this method requires the exception object to be raised during the execution of a hardware assisted transaction, and as a result of determining that the transaction should be rolled back, marshaling the exception objects out of the transaction.

TL;DR: In this paper, the authors describe techniques for generating invocation stubs for a data parallel programming model so that a data-parallel program written in a statically-compiled high-level programming language may be more declarative, reusable and portable than traditional approaches.

TL;DR: In this paper, a cache resident transaction with nested structured parallelism construct is handled, and a determination is made as to whether the transaction would run faster serially in cache resident mode or faster parallel in software transactional memory mode for the overall transaction.