One of the most concerning issues in current video coding systems relies on the bottleneck caused by the intense external memory access required by motion estimation. As memory access affects directly the energy consumption, this problem becomes more evident when battery-powered devices are considered. In this sense, this article presents the Double Differential Reference Frame Compressor (DDRFC), which is a low-complexity and lossless solution to compress the reference frames before storing them in the external memory. The DDRFC performs intra-block double differential coding over 64 × 64-sample blocks to prepare the data for a static Huffman coding. The DDRFC guarantees block-level random access by avoiding data dependencies between neighboring blocks. It reaches an average compression ratio of 69 % for luminance samples for 1080 p video sequences, outperforming any lossless reference frame compressor available in the current literature. Hardware architectures for both the DDRFC encoder and decoder were designed and synthesized targeting FPGA and ASIC 180 and 65-nm standard cells libraries. The synthesis results show that with 65 nm, the DDRFC architectures are able to process 2160 p video at 30 FPS or 1080 p at 120 FPS with a power dissipation of 5.01 mW. The DDRFC codec reaches more than 68 % of energy savings when considering memory communication for HD and UHD video processing.

Efficient reference frame compression scheme for video coding systems: algorithm and VLSI design

This paper presents and evaluates four weighting schemes for image interpolation algorithms. The first scheme is based on the normalized area of the circle, whose diameter is equal to the minimum side of a tetragon. The second scheme is based on the normalized area of the circle, whose radius is equal to the hypotenuse. The third scheme is based on the normalized area of the triangle, whose base and height are equal to the hypotenuse and virtual pixel length, respectively. The fourth weighting scheme is based on the normalized area of the circle, whose radius is equal to the virtual pixel length-based hypotenuse. Experiments demonstrated debatable algorithm performances and the need for further research.

Normalized Weighting Schemes for Image Interpolation Algorithms.

Image interpolation algorithms pervade many modern image processing and analysis applications. However, when their weighting schemes inefficiently generate very unrealistic estimates, they may negatively affect the performance of the end-user applications. Therefore, in this work, the author introduced four weighting schemes based on some geometric shapes for digital image interpolation operations. Moreover, the quantity used to express the extent of each shape’s weight was the normalized area, especially when the sums of areas exceeded a unit square size. The introduced four weighting schemes are based on the minimum side-based diameter (MD) of a regular tetragon, hypotenuse-based radius (HR), the virtual pixel length-based height for the area of the triangle (AT), and the virtual pixel length for hypotenuse-based radius for the area of the circle (AC). At the smaller scaling ratio, the image interpolation algorithm based on the HR scheme scored the highest at 66.6% among non-traditional image interpolation algorithms presented. However, at the higher scaling ratio, the AC scheme-based image interpolation algorithm scored the highest at 66.6% among non-traditional algorithms presented, and, here, its image interpolation quality was generally superior or comparable to the quality of images interpolated by both non-traditional and traditional algorithms. 

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Normalized Weighting Schemes for Image Interpolation Algorithms

Video compression performance of High Efficiency Video Coding (HEVC) is about twice of H.264/AVC video compression standard. The improvement in coding efficiency in HEVC is achieved by considerable increase in the computational load compared to H.264/AVC which is substantially very computational intensive. One of the units in HEVC which has changed considerably compared to H.264/AVC is Integer Discrete Cosine Transform (IDCT) unit. IDCT in HEVC standard includes 32 × 32, 16 × 16, 8 × 8 and 4 × 4 transforms. In this paper, a hardware solution for implementing the entire inverse IDCTs in HEVC decoder is proposed. The proposed hardware has a resource-sharing pipelined architecture. As a result, the hardware resources and computation time for implementing inverse IDCTs in HEVC decoder are reduced. Synthesis results by using NanGate OpenPDK 45 nm library indicate that the proposed hardware can achieve 222 MHz clock rate and can achieve real-time decoding of 4096 × 3072 video sequences with 70 fps.

Hardware solution for implementing the entire inverse IDCTs in HEVC decoder

Image upscaling is an efficient solution to eliminate the gap between image/video sizes and display resolutions. Generally, image-upscaling algorithms use computation-intensive edge detection and f...

A image-upscaling engine for 1080p to 4k using gradient-based interpolation

Pursuing an experience of high-end visual quality drives human to demand a higher display resolution and a higher frame rate. Hence, a lot of powerful coding tools are aggregated together in emerging video coding standards to improve coding efficiency. This also makes video coding standards suffer from two design challenges: heavy computation and tremendous memory bandwidth. The first issue can be properly solved by a careful hardware architecture design with advanced semiconductor processes. Nevertheless, the second one becomes a critical design bottleneck for a modern video coding system. In this article, a lossless frame recompression using multi-orientation prediction technique is proposed to overcome this bottleneck. This work is realised into a silicon chip with the technology of TSMC 0.18 µm CMOS process. Its encoding capability can reach full-HD (1920 × 1080)@48 fps. The chip power consumption is 17.31 mW@100 MHz. Core area and chip area are 0.83 × 0.83 mm2 and 1.20 × 1.20 mm2, respectively. Exper...

VLSI design of lossless frame recompression using multi-orientation prediction

Video coding systems suffer from tremendous memory bandwidth requirement on external memory. This bandwidth is directly proportional to display resolution and frame rate. The aspiration of high-end visual quality drives display resolution and frame rate upgraded to a certain level. That also causes a design bottleneck on the memory bandwidth of external memory in video coding systems. In this paper, the Multi-Direction Lossless Recompression (MDLR) is proposed to alleviate above issue. It includes two core techniques: (1) Multi-Directional Prediction and (2) Direction-Adaptive Golomb-Rice code. The Multi-Directional Prediction can obtain an efficient residual. Then, Direction-Adaptive Golomb-Rice code converts it into an efficient codeword. The experiment result shows that the proposed MDLR can save the memory bandwidth of the video coding system as high as 42% on average.

An efficient Multi-Directional Lossless Recompression for video coding systems

Generally, the temporal error concealment (TEC) adopts the blocks around the corrupted block (CB) as the search pattern to find the best-match block in previous frame. Once the CB is recovered, it is referred to as the recovered block (RB). Although RB can be the search pattern to find the best-match block of another CB, RB is not the same as its original block (OB). The error between the RB and its OB limits the performance of TEC. The successively temporal error concealment (STEC) algorithm is proposed to alleviate this error. The STEC procedure consists of tier-1 and tier-2. The tier-1 divides a corrupted macroblock into four corrupted 8 × 8 blocks and generates a recovering order for them. The corrupted 8 × 8 block with the first place of recovering order is recovered in tier-1, and remaining 8 × 8 CBs are recovered in tier-2 along the recovering order. In tier-2, the error-adaptive block matching principle (EA-BMP) is proposed for the RB as the search pattern to recover remaining corrupted 8 × 8 bloc...

The successively temporal error concealment algorithm using error-adaptive block matching principle

The sum of absolute difference (SAD) is generally adopted as a cost function in motion estimation (ME) and temporal error concealment (TEC) algorithm owing to its efficiency. The hardware architecture of SAD also consumes considerable power dissipation in video codec chip. Hence, the switching-activity analysis on SAD is quite essential from algorithm/architecture perspectives. This work develops the estimation formulas for switching-activity dedicated for SAD engine according to probability theory. The experiment results reveal that the probability error rate (PER) of the SAD engine is as minor as 5.61%. Consequently, this leads to a precise switching-activity estimation of the SAD-based algorithm/architecture for video signal processing.

Yu-Hsuan Lee

Papers

A image-upscaling engine for 1080p to 4k using gradient-based interpolation

VLSI design of lossless frame recompression using multi-orientation prediction

An efficient Multi-Directional Lossless Recompression for video coding systems

The successively temporal error concealment algorithm using error-adaptive block matching principle

The switching-activity estimation of SAD engine for video coding systems