Showing papers by "Yu Hu published in 2005"

An-OARSMan: obstacle-avoiding routing tree construction with good length performance

Abstract: Routing is one of the important steps in VLSI/ULSI physical design. The rectilinear Steiner minimum tree (RSMT) construction is an essential part of routing. Since macro cells, IP blocks, and pre-routed nets are often regarded as obstacles in the routing phase, obstacle-avoiding RSMT (OARSMT) algorithms are useful for practical routing applications. This paper focuses on the OARSMT problem and presents an algorithm, named An-OARSMan, based on ant colony optimization. A greedy obstacle penalty distance (OP-distance) local heuristic is used in the algorithm and performed on the track graph. The algorithm has been implemented and tested on different kinds of obstacles. Experimental results show that An-OARSMan can handle complex obstacle cases including both convex and concave polygon obstacles with good length performance. It can always achieve the optimal solution in the cases with no more than 7 terminals.

Rectangular steiner tree method of super large size integrated circuit avoiding barrier

Abstract: The obstacle avoiding rectangular Steiner tree method for very large scale integrated circuit (VLSI) design belongs to the field of computer-aided VLSI design technology, and is especially VLSI wiring design. The present invention features the first application of full Steiner tree (FST) end point separating method, subsequent construction of son Steiner tree by means of ant swarm method and voracious FST method for different son sets, and final connection of all the son Steiner trees in detour method. The said algorithm can process multiple end point wire mesh; can process complex obstacles and can process large scale issue in relatively short time. The present invention realizes obstacle avoiding rectangular Steiner tree constructing method with optimized wire length and time efficiency in VLSI wiring design.

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code

Abstract: This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n-1, m, 3) convolutional code is proposed. Theoretic analysis for this encoder is presented to avoid two and any odd erroneous bit cancellations, handle one unknown bit (X bit) and diagnose one erroneous bit. The X-bits tolerance capacity can be enhanced by choosing a proper memory size and weight of check matrix, which can also be obtained by an optimized input assignment algorithm. The theoretic analysis and experimental results on aliasing shows the efficiency of the proposed encoder.

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor

Abstract: This paper presents a decompression architecture using a periodically alterable MUXs decompressor for scan data volume reduction. Compared to static XOR network, the periodically alterable MUXs decompressor has multiple configurations to decode the input information more efficiently. Three different DFT techniques are proposed to handle hard, firm and soft cores, respectively. With the proposed pattern decompression algorithms and scan decompression architecture, smaller test data volume and test application time can be achieved as compared to previous techniques.

Compression/scan co-design for reducing test data volume, scan-in power dissipation and test application time

Abstract: Testing chips is very critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-test technique for LSI design and testing, the need for reducing the test data volume, scan-in power dissipation and test application time (VPT) of the full-scan designed chip is imperative. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme tackling all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3% and 85.5% reduction in test data volume, average scan-in power dissipation, peak scan-in power dissipation and test application time, respectively.

A routing paradigm with novel resources estimation and routability models for x-architecture based physical design

Abstract: The increment of transistors inside one chip has been following Moore's Law. To cope with dense chip design for VLSI systems, a new routing paradigm, called X-Architecture, is introduced. In this paper, we present novel resources estimation and routability models for standard cell global routing in X-Architecture. By using these models, we route the chip with a compensation-based convergent approach, called COCO, in which a random sub-tree growing (RSG) heuristic is used to construct and refine routing trees within several iterations. The router has been implemented and tested on MCNC and ISPD'98 benchmarks and some industrial circuits. The experimental results are compared with two typical existing routers (labyrinth and SSTT). It indicates that our router can reduce the total wire length and overflow more than 10% and 80% on average, respectively.

Right angle wiring tree method for wire length optimized obstacle passing

Abstract: It is a right angle wire tree method of wire optimization and obstacle-avoiding, which is characterized by the following: first to form track graph, then orderly to simplify the non-wire net ends and their relative lines with degree two; then to simplify the wire net ends and their relative lines with degree one to accomplish the track graph simplification; then to use ant group method to from tree to get a complete result of the one track graph; to repeat and iterate the above steps till the maximum time; to find out the optimized result from all the complete results and restore all the wire net ends and their relative lines with degree one to get a complete right angle wire tree.

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores

Abstract: Connection of internal scan chains in core wrapper design (CWD) is necessary to handle the width match of TAM and internal scan chains. However, conventional serial connection of internal scan chains incurs power and time penalty. Study shows that the distribution and high density of don't care bits (X-bits) in test patterns make scan slices overlapping and partial overlapping possible. A novel parallel CWD (pCWD) approach is presented in this paper for lowering test power by shortening wrapper scan chains and adjusting test patterns. In order to achieve shift time reduction from overlapping in pCWD, a two-phase process on test pattern: partition and fill, is presented. Experimental results on d695 of ITC2002 benchmark demonstrated the shift time and test power have been decreased by 1.5 and 15 times, respectively. In addition, the proposed pCWD can be used as a stand-alone time reduction technique, which has better performance than previous techniques.

Via-aware global routing for good VLSI manufacturability and high yield

Abstract: CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in which physical design tool is an essential and critical part. We try to consider the via minimization problem as early as possible in physical design. We propose a routing method focusing on minimizing vias while considering mutability and wire-length constraint. That is, in the global routing phase, we minimize the number of bends, which is closely related to the number of vias. Previous work only dealt with very small nets, but our algorithm is general for the nets with any size. Experimental results show that our algorithm can greatly reduce the count of bends for various sizes of nets while meeting the constraints of congestion and wire-length.

Using MUXs network to hide bunches of scan chains

Abstract: This paper presents a decompression architecture using a periodically alterable MUX network. Compared to the static XOR network, the periodically alterable MUX network has multiple configurations to decode the input information flexibly. Probability analysis can help us to select the proper parameter when considering the DFT schemes. With the dedicated efforts, smaller test data volume and test application time can be achieved compared to previous techniques.

Embedded Test Resource to Reduce the Required Memory and Channels of Tester

Abstract: An embedded test stimulus decompressor is presented to generate the test patterns, which can reduce the required vector memory and channels of automatic test equipment (ATE). The decompressor consists of a periodically alterable MUX network which has multiple configurations to decode the input information flexibly. A complete synthesis flow is presented to generate the MUXs network automatically. With the dedicated efforts, the low-cost ATE with low data bandwidth can be used to test the system-on-a-chip with high complexity