On-chip frequency generators for high frequency applications suffer from degradation of key passive components, variable capacitors in particular. In this framework, frequency multipliers can play a key role, allowing the design of voltage-controlled oscillators running at a frequency lower than required with advantage in terms of signal spectral purity and frequency tuning range. In this paper we present two injection locked frequency doublers for Ku-band and F-band applications respectively. Despite differences in implementation details, the same topology where a push-push pair injects a double frequency tone locking an autonomous differential oscillator is adopted. The circuits require limited input signal swing and provide a differential output over a broad frequency range. Dissipating 5.2 mW, the Ku-band multiplier, realized in a 0.13 μm CMOS node, displays an operation bandwidth from 11 GHz to 15 GHz with a peak voltage swing on each output of 470 mV. The F-band multiplier, realized in 65 nm CMOS technology, displays an operation bandwidth from 106 GHz to 128 GHz with a peak voltage swing on each output of 330 mV and a power dissipation of 6 mW. A prototype including the multiplier, driven by a half-frequency standard LC-tank VCO, demonstrates an outstanding 13.1 % tuning range around 115 GHz.

Injection-Locked CMOS Frequency Doublers for μ-Wave and mm-Wave Applications

This paper presents divide-by-2 and divide-by-3 injection-locked frequency dividers (ILFDs) using a Darlington cell in a TSMC 0.18- $\mu$ m CMOS process. The Darlington cell has higher transconductance than the traditional cross-coupled common source cell for free-running oscillator that reduces the power consumption of ILFDs. Besides, an LC resonance technique is used in the proposed divide-by-2 ILFD to achieve lower power consumption and wide locking range. This work provides an analytic method to choose the injector size for widening the locking range and lowering the power consumption. The measured locking range of the proposed divide-by-2 ILFD is from 20.5 to 22.9 GHz. The measured operation range of the divide-by-3 ILFD is from 24.71 to 28 GHz. The measured phase noises of two dividers under locked condition are ${-}{\hbox{138.3}}$ and ${-}140.35$ dBc/Hz at an offset of 1 MHz when the input referred signals have phase noises of ${-}{\hbox{132.54}}$ and ${-}{\hbox{131.5}}$ dBc/Hz, respectively. Meanwhile, both phase noise differences with respect to injection signal are 5.76 and 8.85 dBc, which are close to the theoretical values of 6 and 9.5 dBc. The core power consumptions are 1.73 and 5.13 mW with the supply voltages of 1.2 and 1.45 V, and the chip sizes are 0.8 $\,\times\,$ 0.75 mm $^{2}$ and 0.77 $\,\times\,$ 0.79 mm $^2$ , respectively.

Designs of K-Band Divide-by-2 and Divide-by-3 Injection-Locked Frequency Divider With Darlington Topology

This paper presents a divide-by-4 (D4) and divide-by-8 (D8) regenerative frequency dividers (RFDs) with the quadrature and the octet outputs. The topologies of the D4 and D8 RFDs use the even-harmonic mixers and the current-mode-logic (CML) loop dividers to achieve high division ratio and wide locking ranges. The modified Gilbert cells with quadrature- and octet-phases local-oscillator switching transistors are adopted to perform 2 × and 4 × subharmonic mixing with good conversion efficiency. The divide-by-2 and D4 CML loop dividers are used to obtain wide frequency range and the quadrature and the octet outputs. The D4 and D8 RFDs were fabricated by using a 90-nm CMOS process. With consuming 10.8 and 17.8 mW of dc power, the measured locking ranges of the D4 and D8 dividers are 13.2-18.4 and 16.8-26 GHz, respectively. Over the whole locking range, the two dividers with the phase deviation between the quadrature and the octet signals to be less than 2.2° and 4.4°, respectively. The proposed circuits achieve wide locking ranges and accurate output phases, making them very attractive for application into a multi-phase generator.

Wide-Locking-Range Multi-Phase-Outputs Regenerative Frequency Dividers Using Even-Harmonic Mixers and CML Loop Dividers

This letter presents a wide locking range divide-by-4 LC injection-locked frequency divider (ILFD) implemented in the TSMC 0.18- $\mu \text{m}$ 1P6M CMOS process. The single-stage divide-by-4 ILFD uses harmonic mixer and overlapped locking ranges to emulate a wide locking range. At the drain–source bias of 0.8 V, the ILFD-core power consumption is 7.09 mW. At the incident power of 0 dBm, the maximum locking range of the divide-by-4 ILFD is 6 GHz (37.5%) from 13 to 19 GHz. The ILFD comprises a capacitive cross-coupled nMOS pair and two shunt fourth-order RLC resonators. The die area is $1.008\times1.182$ mm $^{{{2}}}$ .

Wideband Divide-by-4 Injection-Locked Frequency Divider Using Harmonic Mixer

An innovative mixer architecture using gate- and drain-pumped with combining drain terminals of nMOS transistors is proposed to enhance IF and local oscillator (LO) operation bandwidths in 90-nm CMOS for astronomical application. With 0.6 mW of dc power, this mixer achieved peak conversion gains of −6.2, −6.1, −8.6, and −7.2 dB at LO frequencies of 30, 50, 60, and 90 GHz, respectively. At an LO power of 2.3 dBm and an LO frequency of 30 GHz, the IF 3-dB bandwidth is 26 GHz. When the LO power is 4.2 dBm at an LO frequency of 90 GHz, the mixer has an IF 3-dB bandwidth of 16 GHz. The IP 1dB (input 1-dB gain compression) is better than 2 dBm from 30 to 90 GHz. The chip occupies an area of 0.389 mm2. Compared with other published works, this mixer demonstrates a breakthrough for extremely wide IF and LO bandwidths in low dc power consumption with high IP 1dB.

A Novel 30–90-GHz Singly Balanced Mixer With Broadband LO/IF

This letter presents a 5 to 45 GHz broadband distributed mixer implemented by using a standard 0.18 μm CMOS process. The proposed mixer uses a cascoded complementary switching pair to improve port-to-port isolation. The proposed mixer also forms a four-stage distributed topology to achieve a broad bandwidth and reduce conversion loss (CL). The distributed mixer achieves a wide operation bandwidth from 5 to 45 GHz; a low CL of 11 to 13.2 dB; good LO-to-RF, LO-to-IF, and RF-to-IF isolations from 33 to 47 dB, 28 to 53 dB, and 32 to 48 dB, respectively, at an LO power level of 8 dBm with a low 1.4 mW dc power consumption.

A 5 to 45 GHz Distributed Mixer With Cascoded Complementary Switching Pairs

This letter presents a current-mode-logic (CML) ring oscillator integrated with two frequency triplers for quadrature local-oscillator generation. Quadrature signals and frequency-doubled signals of the CML ring oscillator are propagated to drive two single-balanced mixers for up-converting the frequency by triple and achieving quadrature output and low power consumption. Fabricated by a TSMC 90 nm CMOS technology, the proposed circuit consumed 8.7 mW dc power at a 1.2 V supply voltage and achieved an output frequency of 16.56 to 19.8 GHz (17.8%) at a Vtune of 0 to 1.2 V. The phase noise of - 104.6 dBc/Hz was measured from the output signal at a 1 MHz offset frequency. A remarkable figure of merit with a tuning range evaluated at - 188.4 was also obtained.

A Low-Power Quadrature Local Oscillator Using Current-Mode-Logic Ring Oscillator and Frequency Triplers

A divide-by-four transformer-coupled regenerative frequency divider implemented by a TSMC 90 nm CMOS process is presented. A transformer-coupling technique and a source-injected current-mode-logic divider were proposed to increase the injection signal level and widen the operation range of the loop divider. A subharmonic mixer with bottom-switching pairs was used to reduce dc power consumption and optimize the conversion gain. The divider core consumes 6.8 mW at 1.2 V supply voltage. Without using the tuning techniques, the measured locking range is 4.7 GHz (20.9%) from 20.1 to 24.8 GHz. The phase deviation of the quadrature output is less than 0.72 °.

A Divide-by-Four Transformer-Coupled Regenerative Frequency Divider With Quadrature Outputs

The ÷ 3 and ÷ 5 regenerative frequency dividers (RFDs) with ultra-wide locking ranges are presented. The proposed dividers were fabricated by a TSMC 90 nm CMOS process, using ÷ 2 and ÷ 4 quadrature-injected current-mode-logic loop dividers to widen the locking ranges. The dividers also achieved quadrature input and quadrature output. Using a 1.2 V supply voltage, the power consumptions of the ÷ 3 and the ÷ 5 divider cores were 10.2 and 14.8 mW, respectively. Without using the tuning techniques, the measured locking ranges for the ÷ 3 and the ÷ 5 dividers were from 9 to 14.7 GHz (48.1%) and 7.2 to 19 GHz (90.1%), respectively. The phase deviation of the quadrature outputs for the two dividers were less than 0.8 ° and 1.1 °. Compared with the reported data, the outstanding figure-of-merit values of the proposed ÷ 3 and ÷ 5 RFDs can be observed.

Yu-Sheng Lin

Papers

Wide-Locking-Range Multi-Phase-Outputs Regenerative Frequency Dividers Using Even-Harmonic Mixers and CML Loop Dividers

A 5 to 45 GHz Distributed Mixer With Cascoded Complementary Switching Pairs

A Low-Power Quadrature Local Oscillator Using Current-Mode-Logic Ring Oscillator and Frequency Triplers

A Divide-by-Four Transformer-Coupled Regenerative Frequency Divider With Quadrature Outputs

Ultra-Wide Locking Range Regenerative Frequency Dividers With Quadrature-Injection Current-Mode-Logic Loop Divider