A crosspoint matrix switching element and associated method for a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 13401,1, 13402,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 11151, 11152, . . . , 1115K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (2781, 2782, . . . , 278N) of the switch. The switching element includes a control circuit which compares corresponding bits of two incoming bit streams in specific time windows to generate control signals and a routing circuit responsive to the control signals for routing the two input bit streams alternatively to two data outputs.

Crosspoint matrix switching element for a packet switch

An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

ATM switching system and cell control method

A method and apparatus for a high speed asynchronous transfer mode switch is provided which includes an input buffer circuit coupled to communication lines for receiving and temporarily storing packets from the communication lines, a switch comprising one or more planes and output circuitry for coupling the switch outputs to respective communication lines. The switch is comprised of a plurality of switching elements, each of which include a sorter for ranking packets responsive to addresses associated with the packets, compare circuitry for receiving the ranked packets from the sorter and passing up to a predetermined number of packets having the same address, and routing circuitry for routing the packets passed by the compare circuitry responsive to the associated addresses. After a packet is successfully transferred through the switch, an acknowledge signal is returned to the sending input buffer circuit.

Method and apparatus for a high speed asynchronous transfer mode switch

Routing of packets in a packet cross-connect switch is determined based on the particular type of packet, i.e., statistical or periodic, grade of service assigned to the packet, e.g., minimum delay, the actual queuing delay at output assigned to the particular packet destination and the status of the assigned output ports. Additionally, for periodic type packets the routing decision is also based on whether an interval is reserved for transmission of periodic packets at the assigned output ports. The routing decision is also based under certain conditions on whether or not the packet has been previously scheduled over an alternate route. The actual queuing delay at the assigned output ports is compared to predetermined delay threshold values in determining the packet route and/or whether it should be discarded. If the packet is a statistical type and it was previously scheduled over an alternate route, it will be discarded, if it is not scheduled to be routed via a primary one of the assigned output ports and the delay at a secondary, i.e., alternate, one of the assigned output ports is greater than a predetermined re-routing delay threshold value. In a specific embodiment, the delay threshold values are selected such that typically only statistical packets are scheduled for an alternate route. Periodic packets are typically scheduled for an alternate route or discarded only for catastrophic failures.

Packet route scheduling in a packet cross connect switch system for periodic and statistical packets

A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells. Each cell communicates with at least one other cell of the array, thereby permitting an exchange of data packets to take place between the cells of the array. Each cell includes a memory for receiving a data packet from another cell of the array as well as a control entity to control release of a data packet toward a selected destination cell of the array at least in part on a basis of a degree of occupancy of the memory in the destination cell. In this way, scheduling is distributed amongst the cells of the switch fabric.

Cell-based switch fabric with distributed scheduling

This invention is large N×N packet switch, formed using a plurality of smaller packet switches. The invention comprises an N input, L output interconnect fabric (L>N), and a plurality of J×K smaller packet switches (J>K). Each of the J inputs to each packet switch is connected to a separate one of the L outputs of the interconnect fabric, and each of the K outputs from each packet switch is connected to a destination equipment. In operation, packets are received at the N inputs to the interconnect fabric, and each packet is routed to one of the inputs of the packet switch associated with the destination user equipment for the packet. Simultaneous packets, up to J in number, are routed to separate inputs of a particular packet switch for distribution to their respective destinations, while all other simultaneous packets destined for user equipments associated with the same packet switch are lost, the probability of such a loss being acceptably small.

Growable packet switch architecture

This invention is an inventive N input by L output interconnect fabric. In operation, packets comprising an information field and an address are received at the N inputs to the interconnect fabric, and the address in each packet is mapped to a group of outputs, rather than to any particular output. Each packet is then routed to any available one of the interconnect fabric outputs associated with the group to which the packet is mapped. If a number of packets destined for the same group simultaneously arrive at the interconnect fabric inputs and the group to which they are all destined does not comprise enough outputs to accept them, then all packets in excess of the number that the destined group can accept are simply discarded. The probability of lost jackets due to such discarded packets is acceptably small. In one exemplary embodiment, the invention can be utilized to build arbitrarily large packet switches.

Yu Shuan Yeh

Papers

Growable packet switch architecture

Interconnect fabric providing connectivity between an input and arbitrary output (s) of a group of outputs