Insulated-gate GaN-based transistors can fulfill the emerging demands for the future generation of highly efficient electronics for high-frequency, high-power and high-temperature applications. However, in contrast to Si-based devices, the introduction of an insulator on (Al)GaN is complicated by the absence of a high-quality native oxide for GaN. Trap states located at the insulator/(Al)GaN interface and within the dielectric can strongly affect the device performance. In particular, although AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) provide superior properties in terms of gate leakage currents compared to Schottky-gate HEMTs, the presence of an additional dielectric can induce threshold voltage instabilities. Similarly, the presence of trap states can be detrimental for the operational stability and reliability of other architectures of GaN devices employing a dielectric layer, such as hybrid MIS-FETs, trench MIS-FETs and vertical FinFETs. In this regard, the minimization of trap states is of critical importance to the advent of different insulated-gate GaN-based devices. Among the various dielectrics, aluminum oxide (Al2O3) is very attractive as a gate dielectric due to its large bandgap and band offsets to (Al)GaN, relatively high dielectric constant, high breakdown electric field as well as thermal and chemical stability against (Al)GaN. Additionally, although significant amounts of trap states are still present in the bulk Al2O3 and at the Al2O3/(Al)GaN interface, the current technological progress in the atomic layer deposition (ALD) process has already enabled the deposition of promising high-quality, uniform and conformal Al2O3 films to gate structures in GaN transistors. In this context, this paper first reviews the current status of gate dielectric technology using Al2O3 for GaN-based devices, focusing on the recent progress in engineering high-quality ALD-Al2O3/(Al)GaN interfaces and on the performance of Al2O3-gated GaN-based MIS-HEMTs for power switching applications. Afterwards, novel emerging concepts using the Al2O3-based gate dielectric technology are introduced. Finally, the recent status of nitride-based materials emerging as other gate dielectrics is briefly reviewed.

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Status of Aluminum Oxide Gate Dielectric Technology for Insulated-Gate GaN-Based Devices

Thermoreflectance-based techniques, such as pump–probe thermoreflectance (pump–probe TR) and thermoreflectance thermal imaging (TTI), have emerged as the powerful and versatile tools for the characterization of wide bandgap (WBG) and ultrawide bandgap (UWBG) semiconductor thermal transport properties and device temperatures, respectively. This Review begins with the basic principles and standard implementations of pump–probe TR and TTI techniques, illustrating that when analyzing WBG and UWBG materials or devices with pump–probe TR or TTI, a metal thin-film layer is often required. Due to the transparency of the semiconductor layers to light sources with sub-bandgap energies, these measurements directly on semiconductors with bandgaps larger than 3 eV remain challenging. This Review then summarizes the general applications of pump–probe TR and TTI techniques for characterizing WBG and UWBG materials and devices where thin metals are utilized, followed by introducing more advanced approaches to conventional pump–probe TR and TTI methods, which achieve the direct characterizations of thermal properties on GaN-based materials and the channel temperature on GaN-based devices without the use of thin-film metals. Discussions on these techniques show that they provide more accurate results and rapid feedback and would ideally be used as a monitoring tool during manufacturing. Finally, this Review concludes with a summary that discusses the current limitations and proposes some directions for future development.

A review of thermoreflectance techniques for characterizing wide bandgap semiconductors’ thermal properties and devices’ temperatures

In this paper, thermoreflectance microscopy was used to measure the high spatial resolution temperature distribution of the p-GaN HEMT under high power density. The maximum temperature along the GaN channel was located at the drain-side gate edge region. It was found that the thermal resistance (Rth) of the p-GaN HEMT device increased with the increase of channel temperature. The Rth dependence on the temperature was well approximated by a function of Rth~Ta (a = 0.2). The three phonon Umklapp scattering, point mass defects and dislocations scattering mechanisms are suggested contributors to the heat transfer process for the p-GaN HEMT. The impact of bias conditions and gate length on the thermal characteristics of the device was investigated. The behaviour of temperature increasing in the time domain with 50 µs pulse width and different drain bias voltage was analysed. Finally, a field plate structure was demonstrated for improving the device thermal performance. 

/pdf/investigation-on-the-thermal-characteristics-of-enhancement-idvlzh5f.pdf

Investigation on the Thermal Characteristics of Enhancement-Mode p-GaN HEMT Device on Si Substrate Using Thermoreflectance Microscopy

We designed a high electron mobility transistor (HEMT) epitaxial structure based on an AlGaN/GaN heterojunction, utilizing Silvaco TCAD, and selected AlGaN with an aluminum composition of 0.1 as the back-barrier of the AlGaN/GaN heterojunction. We enhanced the confinement of the two-dimensional electron gas (2DEG) by optimizing the structural parameters of the back barrier, so that the leakage current of the buffer layer is reduced. Through these optimization methods, a lower drain leakage current and a good radio frequency performance were obtained. The device has a cut-off frequency of 48.9 GHz, a maximum oscillation frequency of 73.20 GHz, and a radio frequency loss of 0.239 dB/mm (at 6 GHz). This work provides a basis for the preparation of radio frequency devices with excellent frequency characteristics and low RF loss.

https://www.mdpi.com/2072-666X/13/6/830/pdf?version=1653556733

Reduction in RF Loss Based on AlGaN Back-Barrier Structure Changes

Due to an increasing demand of developing III-nitride optoelectronics on silicon substrates, it is necessary to compare the growth and optical properties of III-nitride optoelectronics such as InGaN based light emitting diodes (LEDs) on silicon substrates and widely used sapphire substrates. GaN-on-silicon suffers from tensile strain, while GaN-on-sapphire exhibits compressive strain. This paper presents a comparative study of InGaN/GaN multiple quantum wells (MQWs) grown on a silicon substrate and a sapphire substrate under identical conditions. It has been found that GaN strain status has a significant influence on the growth and the optical properties of InGaN/GaN MQWs. Photoluminescence measurements indicate the InGaN/GaN MQWs grown on a silicon substrate exhibit significantly longer wavelength emission than those on a sapphire substrate. Detailed x-ray diffraction measurements including reciprocal space mapping measurements confirm that both indium content and growth rate in the InGaN MQWs on the silicon substrate are enhanced due to the tensile strain of the GaN underneath compared with those on the sapphire substrate. This work also presents an investigation on strain evolution during the InGaN MQWs growth on the two different kinds of substrates. A qualitative study based on in-situ curvature measurements indicates that a strain change on the silicon substrate is much more sensitive to a growth temperature change than that on the sapphire substrate. It is worth highlighting that the results provide useful guidance for optimising growth conditions for III-nitrides optoelectronics on silicon substrates.

A comparison study of InGaN/GaN multiple quantum wells grown on (111) silicon and (0001) sapphire substrates under identical conditions

GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.

Yu-Wen Huang

Papers

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration.