Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.

Time-to-digital converter

Wireless communication technology continues to advance at a rapid pace, and researchers have made tremendous progress in extending single-input single-output (SISO) systems to multiple-input multiple-output (MIMO) systems such as IEEE 802.11n, WiMAX, and LTE. However, a MIMO system requires a detector circuit to separate received data. To reduce the number of comparators required, the method of modified merge sort is proposed, and the results are compared with those of five sorting algorithms. This modified merge sort requires approximately 56% fewer comparators than a bitonic merge sort and approximately 46% fewer comparators than an odd-even merge sort. When implemented in a TSMC 0.18-μm process, the proposed chip demonstrates a throughput of up to 1200 Mbps at an operating frequency of 150 MHz.

Implementation of a High-Throughput Modified Merge Sort in MIMO Detection Systems

The emerging millimeter-wave (mm-wave) MIMO systems are subject to strong radio frequency (RF) distortions and their compensation is crucial to realize such systems. In the existing literature, several estimation and compensation schemes have been proposed for RF distortions, such as carrier frequency offset, phase noise, and in-phase and quadrature amplitude and phase imbalance (IQI). However, in-phase and quadrature timing mismatch (IQTM) is largely ignored. This paper investigates the effect of the IQTM on mm-wave system performance and reveals that IQTM causes a specific image rejection ratio characteristic, which is substantially different from the regular frequency-dependent IQI and it substantially prolongs the effective channel length. If not compensated, the IQTM can degrade system performance significantly. As a solution to this IQTM problem, this paper proposes novel pilot designs for transmit and receive IQTM estimation, and develops corresponding estimators, transmission protocol, and compensation schemes. MIMO averaging is also proposed, which substantially enhances the IQTM estimation performance. Simulation results show that our proposed pilot designs and estimators offer an efficient solution to the IQTM problem.

In-Phase and Quadrature Timing Mismatch Estimation and Compensation in Millimeter-Wave Communication Systems

This paper presents a tracking and detection engine for 2 $\times$ 2 spatial-multiplexing multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems under highly time-selective fading channels. A recursive least-squares (RLS) adaptive algorithm is adopted to track time-varying channel frequency response. Besides, iterative MIMO signal detection is used, including inter-carrier interference (ICI) cancellation, to enhance system performance. To avoid error propagation in the decision-directed RLS adaptation, ordered-selection mechanism and signal strength criteria are incorporated so that more reliable detection results can be selected for calculating channel statistics. The scheduling strategies and hardware reduction techniques are proposed for implementation of the computation-intensive RLS adaptive algorithm and ICI cancellation. This baseband processor has been fabricated in 90 nm CMOS technology and has 1023K gates. At the nominal operating frequency of 15.36 MHz, it provides throughput of 76.8 Mbps with 64-QAM up to 240 Km/hr. For constellation of 16-QAM and QPSK, the mobility of 360 Km/hr is supported. The power consumption is 11.8 mW at 0.7 V supply voltage. The operating frequency can be raised up to 103 MHz to offer 515 Mbps throughput with power consumption of 202 mW at 1.2V.

An RLS Tracking and Iterative Detection Engine for Mobile MIMO-OFDM Systems

Dynamically reconfigurable digital phased array technology has become more common and advances in signal processing techniques have enabled digital self-interference cancellation sufficient for practical simultaneous transmit and receive applications. As systems implement these technologies, techniques for configuring arrays must be developed. In this work, we consider operating an array in an imaging mode and demonstrate the effectiveness of the Fisher Information of a point target's estimated cross-range position in determining the optimal partitioning of an array into transmit and receive elements. We demonstrate that the partitions formed by optimizing the Fisher Information metric perform better than those that consider other metrics.

An information-theoretic approach to partitioning simultaneous transmit and receive digital phased arrays

Variations in I/Q gains, phases, and filters of the RF frontend, namely frequency-dependent I/Q imbalance (FDI), are an important factor in OFDM-based wireless access. To enable the proper function of a 4 × 4 MIMO-OFDM receiver this work proposes a low-complexity preamble-assisted solution using only one complex divider and one complex multiplier to handle significant FDI distortions. An all-digital multiphase and multi-rate clock generator (MPRCG) was built to support fast dynamic frequency scaling for FDI estimation and compensation and for efficient implementation. Based on the proposed MPRCG, a skew calibration was also realized to tune I/Q timing coherently via multiphase A/D clocking. Performance evaluation showed that the proposed approach incurs an SNR loss of 1.5 dB to maintain a packet-error rate of less than 10% under a 1 dB gain error, 15 phase error and worse filter mismatch. Thus, this solution not only provides adequate performance, but also makes FDI estimation and compensation more cost-effective.

https://ir.nctu.edu.tw:443/bitstream/11536/22141/1/000322332300023.pdf

A Cost-Effective Preamble-Assisted Engine With Skew Calibrator for Frequency-Dependent I/Q Imbalance in 4 $\,\times\,$ 4 MIMO-OFDM Modem

For enhancing spectrum efficiency, in-band full-duplex technology is one of the candidate technical solution. But, self-interference (SI) signal causes dramatically degrade the performance. In practically, memory effect which cause harmonic in amplifier will be hard to be estimated. Therefore, we utilizes the dynamic regression (DR) to implement digital interference cancellation (DIC) for mitigate the memory effect. Two platforms are constructed to evaluate this mechanism. In both platforms, the SI signal could effectively reduction and the residual signal could be attenuated close to noise floor. In software-defined radio (SDR) platform also proves that the proposed dynamic regression based DIC (DRDIC) is sufficient to attenuate the SI signal, where successfully perform video streaming demonstration.

Digital self-interference cancellation via dynamic regression for in-band full-duplex system

An all-digital clock generator includes a digitally-controlled clock generator and a processing unit. The digitally-controlled clock generator generates a clock signal in response to an enable signal and a digital signal. The processing unit has a frequency multiplier and a reference signal having a period, digitizes the period to generate a quantized signal, generates the digital signal according to the quantized signal and the frequency multiplier, and generates the enable signal according to the reference signal, the clock signal and the frequency multiplier.

https://ir.nctu.edu.tw:443/bitstream/11536/105076/1/20130038349.pdf

Time-to-digital converter and digital-controlled clock generator and all-digital clock generator

In this paper, a single instruction multiple data (SIMD) arithmetic logic unit (ALU)-based architecture is proposed to improve hardware efficiency in a $4 \times 4$ frequency-domain multiple input multiple output–orthogonal frequency division multiplexing modem based on a space-time block code (STBC). The majority of mathematic units in the proposed architecture are centralized so that any mathematic unit can be shared with any algorithm. Six advanced instructions are also defined in the ALU: 1) complex multiplication; 2) complex division; 3) correlation; 4) channel estimation; 5) $4 \times 4$ matrix inversion; and 6) STBC-based decoding. A scheduler is essential to handle all data paths and signaling flows smoothly with the use of an SIMD ALU. As a result, it is relatively easy to reconfigure the proposed design for different specifications. The very large scale integration implementation of this chip, using an in-house 65-nm CMOS process, consumes a total of 1.87 M gates and draws 33.7 mW at a supply voltage of 1 V.

Cost-Efficient Frequency-Domain MIMO–OFDM Modem With an SIMD ALU-Based Architecture

In this paper, we propose a real-time and scalable digital cancellation algorithm to cancel the self-interference signal. We implement this algorithm in the FPGA of NI USRP-2953R platform by using LabVIEW to program it through the PCIe. At the end of this paper, we demonstrate the real-time video stream between two platforms at the central frequency 2.2GHz to 2.5GHz with 20MHz bandwidth in the LTE framework.

Yuan-Te Liao

Papers

A Cost-Effective Preamble-Assisted Engine With Skew Calibrator for Frequency-Dependent I/Q Imbalance in 4 $\,\times\,$ 4 MIMO-OFDM Modem

Digital self-interference cancellation via dynamic regression for in-band full-duplex system

Time-to-digital converter and digital-controlled clock generator and all-digital clock generator

Cost-Efficient Frequency-Domain MIMO–OFDM Modem With an SIMD ALU-Based Architecture

Implementation of digital self-interference cancellation in LTE-based CCFD transmission