The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth-order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure-of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst additionally offering direct integration with digital systems.

/pdf/time-domain-processing-techniques-using-ring-oscillator-3jlphbi9hu.pdf

Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

A quadrature clock corrector uses relaxation oscillators to detect duty-cycle and quadrature phase errors by transforming them into pairs of frequencies, which are then digitized and compared. It achieves good detection accuracy and can detect a wide range of duty-cycle and quadrature phase errors. The prototype is implemented in a 55-nm CMOS process with a supply voltage of 1.2 V and occupies an area of 0.003 mm2. The experimental results show that the operation range is from 1 to 3 GHz, the power efficiency is 0.79 mW/GHz, the maximum duty-cycle error is 0.8% at 3 GHz, and the maximum quadrature phase error is 1.1° at 3 GHz.

A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator

This paper proposes a low-voltage low-power hybrid digital phase-locked loop (LVHDPLL). It adopts a loop bandwidth-tracking technique to keep the loop bandwidth almost constant in order to make the LVHDPLL operate robustly over process, voltage, and temperature variation. We also propose the technique of dynamical control of clock frequency for digital loop filter, and the gated source-switched charge pump to save the power consumption. The LVHDPLL is implemented in a 65-nm CMOS process. It can generate frequency from 0.9 to 2.25 GHz (1.35 GHz) at 0.75-V (0.6 V) supply voltage. The maximum power consumption is 0.43mW at 0.75 V and 0.21 mW at 0.6 V. The power efficiency is 0.191 and 0.156 mW/GHz at 0.75- and 0.6-V supply, respectively. The figure of merit is −228 and −227.4 dB at 0.75- and 0.6-V supply, respectively. The loop bandwidth variation over all covered frequency range is ±7.5%. From 0 °C to 70 °C, the loop bandwidth variation and rms jitter variation are less than 6.1% and 8.8%, respectively. The loop bandwidth variation and rms jitter variation over supply variation (−0.03 to 0.05 V) is less than 7.1% and 9.5%, respectively. This LVHDPLL shows robustness over temperature and supply voltage variation.

A 0.9–2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique

An ultra-low-voltage 8-phase bootstrap (BT) ring-voltage-controlled oscillator (RVCO) exhibiting an improved figure of merit up to 165.2 dBc/Hz is reported. Unlike the existing RVCOs that use single-ended BT inverters with conventional clocks, our RVCO benefits from the inherent non-overlapping clocks of pseudo-differential BT inverters to reduce the charge loss due to asynchronous charge-pump operation, and the phase sensitivity to the transistor noise. They together result in higher oscillation frequency and output swing, while lowering the phase noise. Fabricated in 65-nm CMOS, the BT RVCO measures a phase noise of −93.7 to −92.6 dBc/Hz at a 1-MHz offset from 0.4 to 1.6 GHz, while dissipating 47.4 to $280~\mu\text{W}$ at 0.5 V.

A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM

A low-power wide tuning-range CMOS current-controlled oscillator

This brief describes a pseudodigital oscillator design for low-voltage applications. To overcome the start-up problem of the digitally controlled ring oscillator with an ultralow supply voltage, a digitally controlled relaxation oscillator (DCRXO) that utilizes an inverter-based comparator is proposed. The pseudocomparator (PC), which is a variable threshold inverter, followed by an inverter, is introduced and a digital calibration circuit is used to automatically set the threshold of the PC for process-insensitive operation in the initial state. The DCRXO implemented in 65-nm CMOS consumes 17.8 $\mu\mbox{W} $ from a 0.35-V supply at 26-MHz output and achieves a tuning range of 18.2–29.2 MHz with a sufficient overlap between tuning curves. The phase noise of −104 dBc/Hz at 1 MHz offset is measured at 26-MHz output frequency. When the supply voltage of 0.5 V is used, the DCRXO consumes 59 $\mu\mbox{W} $ at 100-MHz output with the tuning range of 43.5–152 MHz. The core area of the DCRXO is 0.0362 mm2.

A 0.35–0.5-V 18–152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS

A 0.55V 100MHz LDO-embedded ADPLL is implemented in 65nm CMOS. A digitally-controlled relaxation oscillator (DCRXO) with a variable-threshold inverter and a digital calibration circuit is designed for robust start up under ultra-low supply voltage. A ΔΣ modulated pseudo-digital LDO provides a PVT-insensitive dithered internal voltage for the DCRXO. The 100MHz ADPLL including the LDO consumes a 67μW from a 0.55V supply and achieves the phase noise of −82.9dBc/Hz at 1MHz offset frequency. The LDO achieves >20dB PSRR when sinusoidal noise is injected to the supply.

A 0.55V 100MHz ADPLL with ΔΣ LDO and Relaxation DCO in 65nm CMOS

A chirp-UWB transceiver which transmits a 1.3 bit information in a single pulse clock period by embedding pulse position information in the chirp FSK modulation is implemented in 0.18μm CMOS. A digital-intensive chirp-UWB transmitter by employing digital ramp generator and a digitally-controlled oscillator (DCO) is designed. In the receiver, a dual-BPF based regenerative architecture is employed to relax the Q requirement. The proposed transceiver achieves the energy efficiency of 2.5nJ/b for the transmitter and 24.2nJ/b for the receiver at the data rate of 1.6Mb/s.

Yudong Zhang

Papers

A 0.35–0.5-V 18–152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS

A 0.55V 100MHz ADPLL with ΔΣ LDO and Relaxation DCO in 65nm CMOS

A 1.6Mb/s 3.75–4.25GHz chirp-UWB transceiver with enhanced spectral efficiency in 0.18μm CMOS