Yue Lu

TL;DR: Using a shunt branch in parallel with the differential channel to implement pre-emphasis is shown to have the best overall energy-efficiency, and an efficient pre- emphasis voltage mode transmitter architecture with output amplitude control, pre-phasis coefficient control, and online impedance calibration is proposed and demonstrated.

TL;DR: BAG is introduced, the Berkeley Analog Generator, an integrated framework for the development of generators of Analog and Mixed Signal circuits that will foster design reuse, ease technology migration, and shorten time-to-market, while remaining close to the classical design flow to ease adoption.

TL;DR: This paper analyzes and describes design techniques enabling energy-efficient multi-tap decision feedback equalizers operated at or near the speed limits of the technology and proposes a closed-loop architecture utilizing three techniques, namely a merged latch and summer, reduced latch gain, and a dynamic latch design.

TL;DR: Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate CDR, which saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers.

TL;DR: Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described and current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology.