Showing papers by "Yuriy V. Pershin published in 2023"
3 citations
TL;DR: In this paper , the authors provide a comprehensive roadmap for neuromorphic computing with electron spins, memristive devices, two-dimensional nanomaterials, nanomagnets and assorted dynamical systems.
Abstract: In the Beyond Moore Law era, with increasing edge intelligence, domain-specific computing embracing unconventional approaches will become increasingly prevalent. At the same time, the adoption of a wide variety of nanotechnologies will offer benefits in energy cost, computational speed, reduced footprint, cyber-resilience and processing prowess. The time is ripe to lay out a roadmap for unconventional computing with nanotechnologies to guide future research and this collection aims to fulfill that need. The authors provide a comprehensive roadmap for neuromorphic computing with electron spins, memristive devices, two-dimensional nanomaterials, nanomagnets and assorted dynamical systems. They also address other paradigms such as Ising machines, Bayesian inference engines, probabilistic computing with p-bits, processing in memory, quantum memories and algorithms, computing with skyrmions and spin waves, and brain inspired computing for incremental learning and solving problems in severely resource constrained environments. All of these approaches have advantages over conventional Boolean computing predicated on the von-Neumann architecture. With the computational need for artificial intelligence growing at a rate 50x faster than Moore law for electronics, more unconventional approaches to computing and signal processing will appear on the horizon and this roadmap will aid in identifying future needs and challenges.
3 citations
TL;DR: In this article , the first hardware implementation of a DMM algorithm on a low-cost FPGA board is presented, where the algorithm was partially parallelized to optimize the use of hardware resources.
Abstract: Memcomputing is a novel computing paradigm beyond the von-Neumann one. Its digital version is designed for the efficient solution of combinatorial optimization problems, which emerge in various fields of science and technology. Previously, the performance of digital memcomputing machines (DMMs) was demonstrated using software simulations of their ordinary differential equations. Here, we present the first hardware realization of a DMM algorithm on a low-cost FPGA board. In this demonstration, we have implemented a Boolean satisfiability problem solver. To optimize the use of hardware resources, the algorithm was partially parallelized. The scalability of the present implementation is explored and our FPGA-based results are compared to those obtained using a python code running on a traditional (von-Neumann) computer, showing one to two orders of magnitude speed-up in time to solution. This initial small-scale implementation is projected to state-of-the-art FPGA boards anticipating further advantages of the hardware realization of DMMs over their software emulation.
TL;DR: In this article , the authors introduce a state probability distribution function and associated integro-differential equation to describe the switching process consisting of a set of stochastic jumps, which enables a rigorous description of intrinsic physical behavior not available in other models.
Abstract: Resistance switching memory cells such as electrochemical metallization cells and valence change mechanism cells have the potential to revolutionize information processing and storage. However, the creation of deterministic resistance switching devices is a challenging problem that is still open. At present, the modeling of resistance switching cells is dominantly based on deterministic models that fail to capture the cycle-to-cycle variability intrinsic to these devices. Herewith we introduce a state probability distribution function and associated integro-differential equation to describe the switching process consisting of a set of stochastic jumps. Numerical and analytical solutions of the equation have been found in two model cases. This work expands the toolbox of models available for resistance switching cells and related devices, and enables a rigorous description of intrinsic physical behavior not available in other models.
TL;DR: The leaky memcapacitor as discussed by the authors is a movable-plate capacitor that becomes quite conductive when the plates come close to each other, which is useful for the hardware implementation of spiking neurons.
Abstract: In this article, we introduce a new nanoscale electromechanical device -- a leaky memcapacitor -- and show that it may be useful for the hardware implementation of spiking neurons. The leaky memcapacitor is a movable-plate capacitor that becomes quite conductive when the plates come close to each other. The equivalent circuit of the leaky memcapacitor involves a memcapacitive and memristive system connected in parallel. In the leaky memcapacitor, the resistance and capacitance depend on the same internal state variable, which is the displacement of the movable plate. We have performed a comprehensive analysis showing that several spiking types observed in biological neurons can be implemented with the leaky memcapacitor. Significant attention is paid to the dynamic properties of the model. As in leaky memcapacitors the capacitive and leaking resistive functionalities are implemented naturally within the same device structure, their use will simplify the creation of spiking neural networks.