Full-chip capacitance extraction programs based on lookup techniques, such as HILEX/CUP , can be enhanced to rigorously account for process variations in the dimensions of very large scale integration interconnect wires with only modest additional computational effort. HILEX/CUP extracts interconnect capacitance from layout using analytical models with reasonable accuracy. These extracted capacitances are strictly valid only for the nominal interconnect dimensions; the networked nature of capacitive relationships in dense, complex interconnect structures precludes simple extrapolations of capacitance with dimensional changes. However, the derivatives, with respect to linewidth variation of the analytical models, can be accumulated along with the capacitance itself for each interacting pair of nodes. A numerically computed derivative with respect to metal and dielectric layer thickness variation can also be accumulated. Each node pair's extracted capacitance and its gradient with respect to linewidth and thickness variation on each metal and dielectric layer can be stored in a file. Thus, instead of storing a scalar value for each extracted capacitance, a vector of 3I+1 values will be stored for capacitance and its gradient, where I is the number of metal layers. Subsequently, this gradient information can be used during circuit simulation in conjunction with any arbitrary vector of interconnect process variations to perform sensitivity analysis of circuit performance.

Rapid method to account for process variation in full-chip capacitance extraction

A ring oscillator based variation test chip

We present a sensitivity study approach to evaluate the effects of interconnect variations on the performance of large, complex circuits. The approach uses highly efficient designed experiments. The results from the study of a multiplier circuit are presented as an example.

https://ieeexplore.ieee.org/iel4/5907/15752/00729773.pdf

Sensitivity study of interconnect variation using statistical experimental design

VLSI interconnect capacitance is becoming more significant and also increasingly subject to process variation. A simple technique to extract from layout the sensitivity of interconnect parasitic capacitance to linewidth process variations is proposed based on 2.5D capacitance models and implemented in the Magic VLSI layout editor. The derivative of each extracted capacitance with respect to variation in every level is obtained. Coincident edges in layout result in distinct “shrinking” and “bloating” derivatives. The derivatives form a gradient that may be multiplied by a vector of the variations on each level to give the total expected deviation from nominal capacitance. The gradient allows the process sensitivity of each capacitance to be determined by simply inspecting the netlist.

Extracting interconnect capacitance sensitivity to linewidth variation

Deep submicron technology makes interconnect one of the main factors determining the circuit performance. Previous work shows that interconnect parameters exhibit a significant amount of spatial variation. In this work, we present a methodology to study the influence of the interconnect variation on circuit performance. Parameterized interconnect modeling technology is introduced, and a ring oscillator circuit with interconnect dominant loading is studied.

Z.J. Lin

Papers

Study of circuit sensitivity to interconnect variation