We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.

Area-efficient linear regulator with ultra-fast load regulation

This paper develops the architecture of a digital PWM controller for application in multiphase voltage regulation modules (VRMs). In this context, passive current sharing and VRM transient response with nonzero controller delay are analyzed. A scheme for sensing a combination of the VRM output voltage and output current with a single low-resolution window analog-to-digital converter (ADC) is proposed. The architecture and IC implementation of a digital PWM (DPWM) generation module, using a ring-oscillator-multiplexer scheme, is discussed. Experimental results from a prototype VRM and a partial controller IC implementation are presented.

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Architecture and IC implementation of a digital VRM controller

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

This paper introduces a voltage mode digital controller for low-power high-frequency DC-DC switch-mode power supplies (SMPS) that has fast transient response, approaching physical limitations of a given power stage. In steady state, the controller operates as a conventional pulsewidth modulation regulator and during transients it utilizes a novel fast voltage recovery mechanism, based on real-time processing of the output voltage in digital domain. This continuous-time digital signal processing mechanism is implemented with a very simple processor consisting of a set of asynchronous comparators, delay cells, and combinatorial logic. To eliminate the need for current measurement and calculate the optimal switching sequence of the power stage transistors, the processor performs a capacitor charge balance algorithm, which is based on the detection of the output voltage peak/valley point. The effectiveness of the controller is demonstrated on an experimental 5 W, 5 V to 1.8 V, 400 kHz buck converter. The converter recovers from load transients through a single on-off action of the power switch, virtually reaching the shortest possible time, limited by the values of the power stage filter components only.

Continuous-Time Digital Controller for High-Frequency DC-DC Converters

This paper develops the architecture of a digital PWM controller for application in multi-phase voltage regulation modules (VRMs) with passive current sharing. In this context, passive current sharing and VRM transient response are analyzed. A scheme for sensing a combination of the VRM output voltage and output current with a single low-resolution windowed analog-to-digital converter (ADC) is proposed. The architecture and IC implementation of a digital PWM (DPWM) generation module, using a ring-oscillator-MUX scheme, is discussed. Experimental results from a prototype VRM and a partial controller IC implementation are presented.

/pdf/architecture-and-ic-implementation-of-a-digital-vrm-2x5u9lkl0e.pdf

The optimized gain of the voltage-error amplifier and current-mode control provide instantaneous transient response and small DC shift of the output voltage for step changes in the load current. This paper analyzes the system, determines the best compensation, provides design guidelines for buck converters powering Pentium(R) II processors and presents results of simulations and experiments.

/pdf/optimizing-the-load-transient-response-of-the-buck-converter-4v9seoooz8.pdf

Z. Zansky

Papers

Optimizing the load transient response of the buck converter