From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

An overview of emerging all-optical networks is given. The characteristics and alternative architectures for single-hop systems are discussed. The characteristics of lightwave technology that facilitate the design of wavelength-division-multiplexing (WDM) networks are reviewed, and it is explained how WDM local networks can be built based on the single-hop and multihop approaches. Various categories of single-hop systems are discussed: experimental systems, systems based on no pretransmission coordination, and systems based on pretransmission coordination, which also require a separate control channel. A simple classification for single-hop systems is provided. >

WDM-based local lightwave networks. I. Single-hop systems

http://eia.udg.es/%7Eqsalvi/papers/2006-MJ.pdf

Review of CMOS image sensors

A survey of communication/networking in Smart Grids

Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage yield-enhancement techniques are aimed at making the integrated circuit "defect tolerant", i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.

/pdf/defect-tolerance-in-vlsi-circuits-techniques-and-yield-42aaq04mxw.pdf

Defect tolerance in VLSI circuits: techniques and yield analysis

It has been recognized that the yield of fault-tolerant VLSI circuits depends on the size of the fault clusters. Consequently, models for yield analysis have been proposed for large-area clustering and small-area clustering, based on the two-parameter negative-binomial distribution. The addition of a new parameter, the block size, to the two existing parameters of the fault distribution is proposed. This parameter allows the unification of the existing models and, at the same time, adds a whole range of medium-size clustering models. Thus, the flexibility in choosing the appropriate yield model is increased. Methods for estimating the newly defined block size are presented and the approach is validated through simulation and empirical data. >

A unified negative-binomial distribution for yield analysis of defect-tolerant circuits

A wavelength division multiplexing (WDM) transmissive star network is investigated, in which each node has one tunable transmitter with limited tuning capability and multiple fixed receivers. Two synchronous channel access protocols requiring no pretransmission penalty are considered: random access and fixed transmission scheduling. An efficient approximate analysis with drastically reduced computational complexity is presented. In spite of the reduced complexity, the presented approach produces very accurate results and can serve in producing the most cost-effective system design for given performance requirements. >

WDM passive star-protocols and performance analysis

Defect maps of 57 wafers containing large area VLSI IC's were analyzed in order to find a good match between the empirical distribution of defects and a theoretical model. Our main result is that the commonly employed models, most notably, the large area clustering negative binomial distribution, do not provide a sufficiently good match for these large area IC's. Only the recently proposed medium size clustering model is close enough to the empirical distribution. An even better match can be obtained either by combining two theoretical distributions or by a "censoring" procedure in which the worst chips are ignored. Another goal of the study was to find out whether certain portions of either the chip or the wafer had more defects than the others. >

A statistical study of defect maps of large area VLSI IC's

Growth of pixel density and sensor array size increases the likelihood of developing in-field pixel defects. An ongoing study on defect development in imagers has now provided us sufficient data to be able to quantify characteristics of defect growth. Preliminary investigations have shown that defects are distributed randomly and the closest distance between two defective pixels is approximately 79-340 pixels apart. Furthermore, from an observation of 98 cluster-free defects, the diameter of the defect is estimated to be less than 2.3% of a pixel size at 99% confidence level. The fact that no defect clusters were found in the study of various digital cameras allows us to conclude that defects are not likely to be related to material degradation or imperfect fabrication but are due to environmental stress such as radiation. Furthermore, as verified by a statistical study, the absence of defect clustering provides information on the size of defects and insight into the nature of the defect development.

Quantitative analysis of in-field defects in image sensor arrays

Although solid-state image sensors are known to develop defects in the field, little information is available about the nature, quantity or development rate of these defects. We report on and algorithm and calibration tests, which confirmed the existence of significant quantities of in-field defects in 4 out of 5 high-end digital cameras. Standard hot pixels were identified in all 4 cameras. Stuck hot pixels, which have not been described previously, were identified in 2 cameras. Previously, hot-pixels were thought to have no impact at short exposure durations, but the large offset of stuck hot pixels will degrade almost any image and cannot be ignored. Fully-stuck and abnormal sensitivity defects were not found. Spatial investigation found no clustering. We tracked hot pixel growth over the lifetime of one camera, using only normal photographs. We show that defects develop continually over the lifetime of the sensor, starting within several months of first use, and do not heal over time. Our success in tracing the history of each defect confirms the feasibility of using automatic defect identification to analyze defect response and growth characteristics in a multitude of cameras already in the field, without performing additional experiments or requiring physical access to the cameras.

Zahava Koren

Papers

A unified negative-binomial distribution for yield analysis of defect-tolerant circuits

WDM passive star-protocols and performance analysis

A statistical study of defect maps of large area VLSI IC's

Quantitative analysis of in-field defects in image sensor arrays

Identification of in-field defect development in digital image sensors