A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Method for fabrication of a semiconductor device and structure

While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford. We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. A Via Patterned Gate Array is proposed as one such example that trades performance for cost by way of new forms of design regularity.

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Exploring regular fabrics to optimize the performance-cost trade-off

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Structured integrated circuit device

A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer.

3D semiconductor device including field repairable logics

It is well recognized that dimensional scaling has reached its diminishing return phase and the industry is now looking to monolithic 3D to be the future technology driver. This was clearly voiced in the Qualcomm keynote at DAC 2014 and follow-on presentation at ISPD 2015. This paper will present a novel use of the ELTRAN® process developed by Canon Inc. about 20 years ago primarily for SOI applications. Using ELTRAN techniques, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without the need to change the current frontline fab process. This flow is further simplified and could be integrated with the game changing monolithic 3D flow introduced last year which leverages the emerging precision bonders, such as EVG's Gemini® XT FB. This flow provides a natural path for product innovation and an unparalleled competitive edge. In addition, this game-changer breakthrough offers a very cost competitive flow.

Modified ELTRAN® — A game changer for Monolithic 3D

It is well recognized that dimensional scaling has reached its diminishing return phase and the industry is now looking to monolithic 3D to be the future technology driver. This was clearly voiced in the Qualcomm keynote at DAC 2014. This paper will present the game changing impact of the emerging precision bonders, such as EVG's Gemini® XT FB. Innovative process flows combined with a 'Smart Alignment' technique could enable any semiconductor vendor to integrate monolithic 3D into its existing manufacturing line and existing process flows with minimal technology challenge. This provides a natural path for product innovation and an unparalleled competitive edge. In sharp contrast, prior published works on monolithic 3D were conditioned on new process flows and new transistor formation recipes. In addition, this game-changer breakthrough offers a very cost competitive flow.

Precision bonders - A game changer for monolithic 3D

A method to form a 3D integrated circuit, the method including: fabricating two or more devices; connecting the devices together to form the 3D integrated circuit, where at least one of the devices has at least one unused designated dice line and at least one of the devices is a configurable device; and interconnecting at least two of the devices using Through Silicon Vias.

Method to form a 3D semiconductor device

A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines, where the second stratum includes a first layer including first transistors and a second layer including second transistors, where the first layer includes a first bus, the first bus interconnecting a plurality of first logic units, where the second layer includes a second bus, the second bus interconnecting a plurality of second logic units.

Zeev Wurman

Papers

3D semiconductor device including field repairable logics

Modified ELTRAN® — A game changer for Monolithic 3D

Precision bonders - A game changer for monolithic 3D

Method to form a 3D semiconductor device

3d semiconductor structure and device