Z
Zewei Shen
Researcher at Huazhong University of Science and Technology
Publications - 30
Citations - 580
Zewei Shen is an academic researcher from Huazhong University of Science and Technology. The author has contributed to research in topics: Pulse-width modulation & Electromagnetic interference. The author has an hindex of 10, co-authored 26 publications receiving 258 citations.
Papers
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Journal ArticleDOI
Dead-Time Effect Compensation Method Based on Current Ripple Prediction for Voltage-Source Inverters
Zewei Shen,Dong Jiang +1 more
TL;DR: This paper introduces a novel DTC method for the VSI which can mitigate the impact of the current ripple and improve the accuracy of DTC, and deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents and the peak values corresponding to rising and falling edges for PWM signals can be predicted.
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Common-Mode Voltage Reduction for Paralleled Inverters
Dong Jiang,Zewei Shen,Fei Wang +2 more
TL;DR: In this article, a novel pulsewidth-modulation (PWM) method for paralleled inverters which can theoretically achieve zero CM voltage is developed, considering the basic voltage vectors in each inverter, novel paralleled voltage vectors which have zero-CM voltage are proposed to combine the reference voltage vector.
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Common-Mode Voltage Elimination for Dual Two-Level Inverter-Fed Asymmetrical Six-Phase PMSM
TL;DR: In this paper, the authors proposed an end-to-end cyclic modulation scheme for the dual two-level inverter-fed asymmetrical six-phase permanent magnet synchronous motor, which has two sets of three-phase windings spatially shifted by 30° electrical degrees.
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A Novel Zero-Sequence Current Elimination PWM Scheme for an Open-Winding PMSM With Common DC Bus
TL;DR: A novel pulsewidth modulation (PWM) scheme for an open-winding permanent magnet synchronous machine (OW-PMSM) driven by dual two-level three-phase inverter with common dc bus which can effectively deal with the inherent zero-sequence current (ZSC) problem.
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Circulating Current Reduction for Paralleled Inverters With Modified Zero-CM PWM Algorithm
TL;DR: In this paper, a modified zero-CMV modulation scheme for paralleled inverters is introduced, which can keep volt-seconds balance in whole fundamental period and mitigate the current jump in phase-leg currents.