The invention discloses a modeling method for parasitic resistance between sources and a substrate and between drains and the substrate in an MOS device. The method comprises the following steps of S01: establishing an equivalent test structure for extracting the parasitic resistance of the MOS substrate, wherein a source quantity ns is equal to a drain quantity nd, the width of each of the sources and the drains is lsd, the distance between two adjacent source and drain is l, and the length of each of the sources and the drains is w; S02: taking a group of w, lsd and ns, changing the size ofl to generate a series of equivalent test structures, and testing resistance values of the corresponding equivalent test structures to determine Rsb, Rdb and Rdsb; S03: transforming layout factors w,lsd and ns, calculating corresponding Rsb, Rdb and Rdsb according to the method in the S02 for each group of w, lsd and ns, and according to different layout factors in the equivalent test structuresand corresponding resistance value change laws, building parasitic resistance models of Rsb, Rdb and Rdsb. According to the modeling method for parasitic resistance between the sources and the substrate and between the drains and the substrate in the MOS device, provided by the invention, the problem of insufficient representation of information by a conventional MOS equivalent test structure is avoided.

Modeling method for parasitic resistance between sources and substrate and between drains and substrate in MOS device

Provided in the embodiments of the present invention are a semiconductor device, a semiconductor chip, and a method for manufacturing the semiconductor device, the semiconductor device comprising a substrate and a semiconductor layer manufactured on the substrate; a plurality of gate electrodes, a plurality of drain electrodes, and a plurality of source electrodes are manufactured on the side of the semiconductor layer furthest from the substrate, the gate electrodes being positioned between the source electrodes and the drain electrodes, and the gate electrodes, the source electrodes, and the drain electrodes being positioned in an active region of the semiconductor device; a gate interval is formed between any two adjacent gate electrodes, the formed gate intervals comprising at least two unequal gate intervals, the biggest gate interval amongst the gate intervals being positioned in a first preset range determined on the basis of the interval in the gate length direction of the two gate electrodes at the outermost two ends of the semiconductor device and the total number of gate electrodes of the semiconductor device. The embodiments of the present invention can effectively improve the temperature distribution gradient in the semiconductor device, increasing the heat dissipation efficiency in the centre of the device.

Semiconductor device, semiconductor chip, and method for manufacturing semiconductor device

The embodiment of the invention provides a semiconductor device, a semiconductor chip and a semiconductor device production method. The semiconductor device comprises a substrate, a semiconductor layer, multiple grids, multiple drains, multiple sources and grid distances, wherein the semiconductor layer is produced based on the substrate; the grids, the drains and the sources are produced based onthe side, away from the substrate, of the semiconductor layer, the grids are located between the sources and the drains, and the grids, the sources and the drains are located in an active region of the semiconductor device; and each grid distance is formed between every two adjacent grids, all the formed grid distances include at least two unequal grid distances, the maximum grid distance among all the grid distances is within a first preset range which is determined according to the distance between the two grids at the two outermost ends in the semiconductor device in the grid length direction and the total quantity of the grids in the semiconductor device. According to the embodiment, a temperature distribution gradient in the semiconductor device can be effectively improved, and the heat dissipation efficiency at the central position of the device is improved.

Semiconductor device, semiconductor chip and semiconductor device production method

The invention provides a modeling method for the layout proximity effect of a multi-interdigital MOS device. The method comprises the following steps: designing a test structure, including a reference device group and a contrast device group for establishing a gate pitch layout proximity effect model; establishing an initial model of a multi-interdigital device without layout proximity effect based on test data of the reference devices, modeling by adopting parallel connection of multiple single-gate MOS devices of which the number is equal to that of interdigital devices; constructing a feature size based on the layout factor related to the gate pitch layout proximity effect of each multi-interdigital MOS device, taking the feature size as a layout factor of the single-gate device in the initial model, and indicating the sum of gate pitch layout proximity effect introduced by all interdigitation of the multi-interdigital device by using the sum of layout proximity effect introduced by all parallel-connected single-gate devices based on the layout factor; and constructing a threshold voltage and mobility correction model according to the feature size, the width and length of single interdigitation and the number of interdigitation to correct the initial model.

Zhou Wei

Papers

Modeling method for layout proximity effect of multi-interdigital MOS device