The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control phys ...

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Integrating MEMS and ICs

The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the More-Than-Moore paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed.

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A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Multi-chip package and method of providing die-to-die interconnects in same

ldquoQuilt packagingrdquo (QP), a new superconnect paradigm for interchip communication, is presented. QP uses conducting nodules that protrude from the vertical facets of integrated circuits to effect a dense, fast, and reduced-power method of interfacing multiple die together within a package or on a multichip module. The concept of QP is presented along with a discussion of advantages over traditional system-on-chip and other system-in-package technologies. A process flow and results of chip fabrication are detailed. Simulations show expected signal propagation between adjacent die of greater than 200 GHz, and measurements of interconnected chips confirming low losses and resonance-free operation to at least 40 GHz have been achieved.

Quilt Packaging: High-Density, High-Speed Interchip Communications

This paper presents a $1\times4$ cavity-backed endfire dipole antenna array based on substrate-integrated suspended line (SISL) platform. A double-side SISL (DSISL) self-packaged feeding network with irregular boundaries is designed for the array. By utilizing the DSISL feeding network, the radiation loss and substrate loss of the feed line are effectively decreased, thus efficiency of better than 91% is achieved. Instead of the conventional metallic cavity, the proposed cavity structure is realized by multiple substrate layers. A predominantly TE10 aperture field is obtained by adjusting the sizes of the backing cavity. Measured results show that the proposed dipole antenna array has narrow beam widths in the E-plane and obtained 10 dB impedance bandwidth of 19.7%, i.e., from 22.77 to 27.75 GHz which can cover the 24 GHz automotive radar band (24.25–26.65 GHz). Moreover, front-to-back ratio of better than 26 dB, high gain of better than 14.1 dBi, and low sidelobe level of better than −15 dB are achieved over the automotive radar frequency band.

A Cavity-Backed Endfire Dipole Antenna Array Using Substrate-Integrated Suspended Line Technology for 24 GHz Band Applications

"Quilt packaging," (QP) a new paradigm for interchip communication, is presented. QP uses conducting modules that protrude from the sides of integrated circuits to affect an enhanced-speed, reduced-power method of interfacing multiple die together within a package or on a multichip module. The concept of QP is introduced along with a discussion of advantages over traditional system-on-chip and system-in-package technologies. Details of a process flow and preliminary results are presented. Simulations show expected signal propagation between adjacent die of greater than 150 GHz

Quilt packaging: a new paradigm for interchip communication

The design and measured performance of an integrated dielectric-filled cavity-backed dipole antenna are presented. For structures integrated into high-epsivr substrates, antennas of this type exhibit decreased surface wave loss and increased air-side directive gain relative to planar antennas. A single-lobe beam with high gain was achieved by designing the backing cavity to excite predominantly TE10 aperture fields. The antennas are suitable for direct integration on dielectric package surfaces for system-in-a-package (SiP) implementations, and can be fabricated using single-side processing. Prototype cavity-backed dipole antennas were measured at Ka band and demonstrated 10 dB boresight directivity and 92% peak radiation efficiency. The impact of cavity design parameters and scalability to MMIC applications are evaluated numerically using three-dimensional (3-D) electromagnetic simulations

High-Gain, High-Efficiency Integrated Cavity-Backed Dipole Antenna at Ka-Band

A dipole antenna backed by a dielectric-filled cavity is proposed that offers reduced surface wave loss and increased air-side directive gain. These antennas are suitable for direct integration on dielectric package surfaces for system-in-a-package (SiP) implementations, and are fabricated using single-side processing. Prototype cavity-backed dipole antennas were measured at 27 GHz and demonstrated a 54% radiation efficiency and 10 dB boresight directivity. Through 3-D electromagnetic simulations, the radiation pattern is found to be mainly determined by cavity geometry while the input impedance is more sensitive to dipole parameters, and the simulations agree well with the measured antenna scattering parameters and radiation patterns.

A Dielectric-filled Cavity-backed Dipole Antenna for Microwave/Millimeter-wave Applications

A physics-based nonlinear equivalent circuit model for coplanar waveguides (CPWs) fabricated on Si substrates has been developed and verified experimentally. In contrast to conventional R-L-C-G models, the proposed model replicates dispersive effects due to finite substrate resistivity using only frequency-independent shunt components, and is suitable for both metal-oxide-semiconductor and direct-contact metal-semiconductor lines. The modeled junction capacitances and conductances show excellent scalability with substrate doping concentration and transmission line geometry. Numerical calculation of the CPW capacitance, based on two-dimensional solutions of Poisson's equation, as well as experimental investigations of the dependence of model parameters on substrate doping and line geometry have been performed. Measurements of typical devices show close agreement between the model prediction and measured transmission line S-parameters from 100MHz to 10GHz.

http://ieeexplore.ieee.org/iel5/7260/32380/01512230.pdf

Zhuowen Sun

Papers

Quilt Packaging: High-Density, High-Speed Interchip Communications

Quilt packaging: a new paradigm for interchip communication

High-Gain, High-Efficiency Integrated Cavity-Backed Dipole Antenna at Ka-Band

A Dielectric-filled Cavity-backed Dipole Antenna for Microwave/Millimeter-wave Applications

Physics-based nonlinear circuit model for coplanar waveguides on silicon substrates