The invention provides a communication method of a CPU and a digital logic module in a PLC system based on SOC FPGA and relates to the communication technology field. According to the method, the FPGAdigital logic is set to be a processor bus secondary device, control registers and data storage areas are constructed in the bus secondary device, the control registers and the data storage areas areread and written through a data bus by the CPU according to the specific sequence to achieve reliable communication with the FPGA logic, and control of a PLC IO device is then completed.

Communication method of CPU and digital logic module in PLC system based on SOC FPGA

The invention relates to the technical field of interface communication, in particular to a communication system and a communication method for POWERPC (Performance Optimization With Enhanced RISC (Reduced Instruction Set Computer)-Performance Computing) and an FPGA (Field-Programmable Gate Array). The system structurally comprises a PowerPC chip and an FPGA chip, wherein the PowerPC chip and theFPGA chip are connected with two GPIOs (General Purpose Input/Output) through a Local Bus; the Local Bus and the GPIOs are connected to control logic in the FPGA chip; the Local Bus is connected to aLocal Bus control module in the FPGA chip; the GPIOs are taken as a handshaking signal to be connected to a read-write control module in the FPGA chip; and the two GPIOs are under a high level by default. The communication system and the communication method for the POWERPC and the FPGA have the characteristic of being simple in implementation, and the data communication of the POWERPC and the FPGA is guaranteed.

Communication system and communication method for POWERPC (Performance Optimization With Enhanced RISC (Reduced Instruction Set Computer)-Performance Computing) and FPGA (Field-Programmable Gate Array)

The invention discloses a communication method between an FPGA and a PC on the basis of a PowerPC and a network port. By means of the method, PowerPC control is not needed in the data transmission process, and an external module is used for controlling. When data is written into an RAM, the external module notifies the PowerPC to process the data through triggered interruption; when the PowerPC needs to transmit the data to a function module, a rising edge is provided for the function module through a GPIO port, and the function module is informed of reading the data. By means of the method, the time expenditure in the data receiving, storing and sending processes is greatly reduced for the PowerPC, and the possibility of communication collapse can be effectively reduced on occasions withhigh instantaneity requirements.

Zou Jiawei

Papers

Communication method between FPGA and PC on basis of PowerPC and network port