Digital Systems Design 

About: Digital Systems Design is an academic conference. The conference publishes majorly in the area(s): Field-programmable gate array & Network on a chip. Over the lifetime, 2188 publications have been published by the conference receiving 18647 citations.

Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core

Abstract: The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption hardware core suited for devices in which low cost and low power consumption are desired. The core constitutes of a novel 8-bit architecture and supports encryption with 128-bit keys. In a 0.13 im CMOS technology our area optimized implementation consumes 3.1 kgates. The throughput at the maximum clock frequency of 153 MHz is 121 Mbps, also in feedback encryption modes. Compared to previous 8-bit implementations, we achieve significantly higher throughput with corresponding area. The energy consumption per processed block is also lower.

A two-step genetic algorithm for mapping task graphs to a network on chip architecture

Abstract: Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient two-step genetic algorithm that has been used to build a tool for mapping an application, described by a parameterized task graph, on to a NoC architecture with a two dimensional mesh of switches as a communication backbone. The computational resources in NoC consist of a set of heterogeneous IP cores. Our algorithm finds a mapping of the vertices of the task graph to available cores so that the overall execution time of the task graph is minimized. We have developed a NoC architecture specific communication delay model to estimate the execution time. Our algorithm is able to handle large task graphs and provide near optimal mapping in a few minutes on a PC platform. Our tool also provides facilities for specifying NoC architecture, generation and viewing synthetic task graphs and viewing the progress of the genetic algorithm as it converges to a solution.

Adaptive Distance Estimation and Localization in WSN using RSSI Measures

Abstract: Localization is one of the most challenging and important issues in wireless sensor networks (WSNs), especially if cost-effective approaches are demanded. In this paper, we present intensively discuss and analyze approaches relying on the received signal strength indicator (RSSI). The advantage of employing the RSSI values is that no extra hardware (e.g. ultrasonic or infra-red) is needed for network-centric localization. We studied different factors that affect the measured RSSI values. Finally, we evaluate two methods to estimate the distance; the first approach is based on statistical methods. For the second one, we use an artificial neural network to estimate the distance.

Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures

Abstract: In this paper, we present a novel fully adaptive and fault-tolerant routing algorithm for Network-on-Chips (NoCs) called Force-Directed Wormhole Routing (FDWR). The proposed routing algorithm is implemented in the switches of a TLM (Transaction Level Model) packet switching NoC using SystemC. Based on these switches, mesh, torus, and hypercube topologies for NoCs can be automatically generated. We show how the proposed algorithm distributes the traffic uniformly across the entire network to avoid overloaded links. Simulation results depict that the proposed routing algorithm is able to route packets even in the case of faulty links or switches in the NoC. Furthermore, it is shown that in the case of faulty switches the area around that switches is not overloaded and that the traffic is uniformly distributed across the entire network.