Showing papers by "Freescale Semiconductor published in 2001"

Lithographic template and method of formation and use

Abstract: The lithographic template is formed having a substrate, an optional etch stop layer formed on a surface of the substrate, and a patterning layer formed on a surface of the etch stop layer. The template is used in the fabrication of a semiconductor device for affecting a pattern in the device by positioning the template in close proximity to the semiconductor device having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template. Radiation is then applied through the template so as to further cure portions of the radiation sensitive material and further define the pattern in the radiation sensitive material. The template is then removed to complete fabrication of the semiconductor device.

Method and system for enabling device functions based on distance information

Abstract: A method, device and computer readable medium for enabling and blocking communications with a remote device based on a distance of the remote device. The method on which the device and computer readable medium are based includes transmitting a message from a local device to a remote device via an ultra wide band (UWB) wireless medium and receiving a response from the remote device via the UWB wireless medium. The transmitting and receiving steps are preferably performed in accordance with a Media Access Control (MAC) protocol. A distance between the local device and the remote device is then determined based on a time between the transmitting of the message and the receiving of the response and a function, such as communicating with the remote device, is performed in the local device based on the distance determined. The communication between the local device and the remote device may be enabled or disabled depending on the distance that the remote device is from the local device. In addition, the distance information for a remote device may be continually updated, or updated only if communication to the remote device are blocked. A positional map may be generated based on distance data determined for a plurality of reference points and the user may select the remote device from the positional map to enable communications to the positional map.

Method of fabricating flux concentrating layer for use with magnetoresistive random access memories

Abstract: A method of fabricating a flux concentrator for use in magnetic memory devices including the steps of providing at least one magnetic memory bit (10) and forming proximate thereto a material stack defining a copper (Cu) damascene bit line (56) including a flux concentrating layer (52). The method includes the steps of depositing a bottom dielectric layer (32), an optional etch stop (34) layer, and a top dielectric layer (36) proximate the magnetic memory bit (10). A trench (38) is etched in the top dielectric layer (36) and the bottom dielectric layer (32). A first barrier layer (42) is deposited in the trench (38). Next, a metal system (29) is deposited on a surface of the first barrier layer (42). The metal system (29) includes a copper (Cu) seed material (44), and a plated copper (Cu) material (46), a first outside barrier layer (50), a flux concentrating layer (52), and a second outside barrier layer (54). The metal system (29) is patterned and etched to define a copper (Cu) damascene bit line (56).

Selective removal of a metal oxide dielectric

Abstract: A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate dielectric layer is then chemically reduced to a metal or a metal hydride. The metal or metal hydride is then removed with a conventional wet etch or wet/dry etch combination. The metal oxide layer may include a metal element such as zirconium, tantalum, hafnium, titanium, or lanthanum and may further include an additional element such as silicon or nitrogen. Reducing the metal oxide layer may includes annealing the metal oxide gate dielectric layer in an ambient with an oxygen partial pressure that is less than a critical limit for oxygen desorption at a given temperature. In another embodiment, reducing the metal oxide gate dielectric layer may include annealing the metal oxide layer while supplying a hydrogen-containing precursor such as silane, ammonia, germane, hydrogen, and hydrazine to the metal oxide gate dielectric layer. The gate electrode may comprise a gate electrode stack that includes a titanium nitride layer over the metal oxide gate dielectric layer and a silicon-containing capping layer over the titanium nitride layer.

Electro-optic structure and process for fabricating same

Abstract: High quality epitaxial layers of oxide can be grown overlying large silicon wafers (22) by first growing an accommodating buffer layer (26) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (24) of silicon oxide. The amorphous intermediate layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous intermediate layer. Waveguides (45) may be formed of high quality monocrystalline material atop the monocrystalline buffer layer. The waveguides can suitably be formed to modulate the wave. Monolithic integration of oxide based electro-optic devices with III-V based photonics and Si circuitry is fully realized.

Integrated impedance matching and stability network

Abstract: An integrated circuit for intermediate impedance matching and stabilization of high power devices is disclosed. High quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates enables the formation of impedance matching and stability circuits to be placed on the same substrate as the active device. Additionally, by using the manifolds of the active to form plates of a capacitor, an impedance matching network of series inductance and shunt capacitor can be compactly fabricated for increasing the output impedance to intermediate levels. The manifolds of the active device are also used to form capacitors to provide stability to high power active devices.

Planar ultra wide band antenna with integrated electronics

Abstract: An planar ultra wide bandwidth (UWB) antenna that provides integration of electronics is disclosed. The antenna has a first balance element that is connected to a terminal at one end. A second balance element is connected to another terminal at one end. The second balance element has a shape that mirrors the shape of the first balance element such that there is a symmetry plane where any point on the symmetry plane is equidistant to all mirror points on the first and second balance elements. Each of the balance elements is made of a generally conductive material. A triangular shaped ground element is situated between the first balance element and the second balance element with an axis of symmetry on the symmetry plane, and oriented such that the base of the triangle is towards the terminals. Accordingly, the ground element and each of the balance elements form two tapered gaps which widen and converge at the apex of the ground element as the taper extends outwardly from the terminals. Under this arrangement, sensitive UWB electronics can be housed within the perimeter of the ground element, thereby eliminating transmission line losses and dispersion, and minimizing and system ringing. A resistive loop connected between the first and second balance elements extends the low frequency response and improves the VSWR. A connection of an array of elements is disclosed that provides a low-frequency cutoff defined by the array size rather than the element size.

Mode controller for signal acquisition and tracking in an ultra wideband communication system

Abstract: A system and method for controlling the mode of operation in a UWB receiver. In one variation, the system and method determines the mode of operation by reading a set number of samples of the signal, estimating mode parameters, calculating a mode probability, and then transitioning in a finite state machine from either a tracking to an acquisition state or vice versa depending on the value of the mode probability. Exemplary versions of the mode controller include a signal to noise ratio calculator, a signal and noise power estimator, and an AGC initialization circuit.

System and method for testing an embedded microprocessor system containing physical and/or simulated hardware

Abstract: A system for testing an embedded system containing a target processor executing a target program and target hardware that may be partially physical and partially simulated. A target monitor determines when the target processor is attempting to access the simulated hardware. This determination is made by monitoring the address bus of the microprocessor to detect an address in the address space of the simulated hardware. An attempt to access the simulated hardware may also be detected by detecting the lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware. In the event of an access to the simulated hardware, a bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator. The hardware simulator processes the data in the same manner that the physical hardware would respond to signals corresponding to the output data. The hardware simulator may also generate data that are converted to corresponding input signals and applied to respective bus connections of the target processor by a bus driver circuit. During the time that output data is being processed by the hardware simulator, execution of the target program by the target processor is suspended, although the target processor may continue to service interrupts.

MEMS variable capacitor with stabilized electrostatic drive and method therefor

Abstract: A micro electro-mechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver ( 120 ) having a driver capacitor of fixed capacitance ( 121 ) in series with a second driver capacitor of variable capacitance ( 126 ). A MEMS variable capacitor ( 130 ) is controlled by applying an actuation voltage potential to the electrostatic driver ( 120 ). The electrostatic driver ( 120 ) and MEMS variable capacitor ( 130 ) are integrated in a single, monolithic device.

Apparatus for fabricating semiconductor structures and method of forming the structures

Abstract: An apparatus (100) and method (800) for forming high quality epitaxial layers of monocrystalline materials grown overlying monocrystalline substrates (310) such as large silicon wafers is provided. The apparatus (100) includes at least two deposition chambers (110) and (140) that are coupled together. The first chamber (110) is used to form an accommodating buffer layer (320) on the substrate (310) and the second (140) is used to form a layer of monocrystalline material (330) overlying the accommodating buffer layer (320).

Semiconductor power device and method of formation

Abstract: In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1090) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1090) impart a lower peak stress than a comparably sized continuous power metal structure (9).

Mram write apparatus and method

Abstract: An MRAM cell and a method of programming the cell are disclosed. The cell includes a free layer of magnetic material having a ferromagnetic resonance with a resonant frequency, the ferromagnetic resonance having a Q greater than one. A hard axis and an easy axis write line are positioned in magnetic communication with the free layer. A cladding layer partially surrounds the hard axis write line and has a similar resonant frequency and with a ferromagnetic resonance Q greater than one. A write signal including the resonant frequency is applied to the hard axis write line and simultaneously a write pulse is applied to the easy axis write line. The Qs of the cell and the cladding layer multiply to substantially increase the switching magnetic field or reduce the current required to provide the same magnetic field.

Multiple level built-in self-test controller and mehod therefor

Abstract: An integrated circuit has a Built-In Self-Test (BIST) controller ( 10 ) that has a sequencer ( 16 ) that provides test algorithm information for multiple memories ( 44, 46, 48, 50 ). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces ( 32, 34, 36, 38 ) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. This timing information is read prior to performing the test algorithm and is used in performing the test algorithm.

Semiconductor device and method therefor

Abstract: A heteroepitaxial structure is made using nanocrystals that are formed closer together than normal lithography patterning would allow. The nanocrystals are oxidized and thus selectively etchable with respect to the substrate and surrounding material. In one case the oxidized nanocrystals are removed to expose the substrate at those locations and selective epitaxial germanium is then grown at those exposed substrate locations. The inevitable formation of the misfit dislocations does minimal harm because they are terminated at the surrounding material. In another case the surrounding material is removed and the germanium is epitaxially grown at the exposed substrate where the surrounding material is removed. The resulting misfit dislocations in the germanium terminate at the oxidized nanocrystals. By using nanocrystals that are able to be formed much closer together than is available for other features through lithography, the misfits are prevented from extending so far as to create harmful threading dislocations.

Floating point multiplier/accumulator with reduced latency and method thereof

Abstract: A circuit (10) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from a critical speed path for dependent calculations. An intermediate representation of a product and a third operand are selectively shifted to facilitate use of prior unnormalized dependent resultants. Logic circuitry (24, 42) implements a truth table for determining when and how much shifting should be made to intermediate values based upon a resultant of a previous calculation, upon exponents of current operands and an exponent of a previous resultant operand. Normalization and rounding may be subsequently implemented, but at a time when a new cycle operation is not dependent on such operations even if data dependencies exist.

Magnetic random access memory having digit lines and bit lines with a ferromagnetic cladding layer

Abstract: A magneto-electronic component includes an electrically conductive layer for generating a magnetic field, a ferromagnetic cladding layer adjacent to the electrically conductive layer, and an antiferromagnetic layer adjacent to the ferromagnetic cladding layer.

Test access mechanism for supporting a configurable built-in self-test circuit and method thereof

Abstract: A configurable test access mechanism has a sliced input wrapper, output wrapper and scan configuration wrapper coupled to a circuit under test The input wrapper efficiently adds a PRPG (pseudo-random pattern generator) function to a scan test structure without impacting speed and power requirements The output wrapper efficiently adds a MISR (multiple input signature register) functionality for additional test purposes to implement a built-in self-test (BIST) apparatus Use of existing scan structures to implement the PRPG and MISR functions provides significant savings of circuitry Variability of test polynomials is easily user programmed

Scan clock circuit and method therefor

Abstract: Embodiments of the present invention relate generally to scan clock waveform generation. One embodiment utilizes global and local circular shift registers to provide a series of shift/capture pulses at a manageable frequency for the tester and launch pulses that are phase shifted in order to provide for at-speed testing. Therefore, scan test patterns may be shifted in or out of state elements at lower frequencies as compared to the normal operating frequency of the integrated circuit being tested, while still allowing for at-speed testing. An alternate embodiment utilizes a circular shift register in combination with static storage devices and waveform generators to provide the shift/capture pulses and launch pulses. Embodiments of the present invention also allow for clock inversion where the clock and clock bar signals are dependent during normal mode and independent during scan test mode.

High K dielectric film and method for making

Abstract: A dielectric layer comprises lanthanum, aluminum and oxygen and is formed between two conductors or a conductor and substrate. In one embodiment, the dielectric layer is graded with respect to the lanthanum or aluminum. In another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer. The dielectric layer can be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

Method of fabricating thermally stable mtj cell and apparatus

Abstract: An MTJ cell (50) including a tunneling layer (64) of material between magnetic material layers (62, 66) with the tunneling layer of material having a greater attraction for a third material than the magnetic material layers. The third material is introduced to one or both so that when the cell is heated the third material is redistributed from the magnetic material layer to the tunneling layer. Upon redistribution the tunneling layer becomes a tunnel barrier material. Also, a first diffusion barrier layer (67) is positioned between a first metal electrode (68) and one of the magnetic material layers (66) and/or a second diffusion barrier layer is positioned between a second metal electrode and the other magnetic material layer to prevent diffusion of the metal in the electrodes into the magnetic material layers.

Method and device for creating and using pre-internalized program files

Abstract: A device (45) receives new program files (46) and uses pre-internalized images to avoid having to internalize a program file every time that program execution occurs. In one embodiment, a software Virtual Machine (50) in the device functions to implement the pre-internalization. Once the program files are pre-internalized to create images that are stored in a permanent memory (56) of the device, the images may subsequently be executed without having to perform a pre-internalization operation. Additionally, use of dynamic memory (52) is reduced in connection with subsequent program execution and execution time of new program files is reduced.

Method of forming a semiconductor device having conductive bumps without using gold

Abstract: A semiconductor device (10) includes a solder bump (40) that is formed using a gold-free under-bump metallurgy (UBM) (21). In a preferred embodiment, UBM (21) includes a diffusion barrier layer (22) of chromium and a metallic layer (24) of copper. The bump layer metallurgy (31) is deposited directly on the metallic layer, without an intervening gold layer. To overcome problems associated with a native oxide layer (26) which forms on the metallic layer, especially on copper, the bump metallurgy includes a seed layer (32) of tin that is deposited prior to a bulk lead layer (34). The bump metallurgy includes a final metallic layer (36) having sufficient tin to make a bump having approximately 97% Pb and 3% tin.

Mixed-signal semiconductor structure, device including the structure, and methods of forming the device and the structure

Abstract: Mixed-signal devices (300) are formed using high quality epitaxial layers of monocrystalline materials grown overlying a monocrystalline substrate such as a large silicon wafer (302), using an accommodating buffer layer (304). The accommodating buffer layer (304) is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide or an amorphous layer formed from a monocrystalline precursor. The device (300) includes passive components (314) formed away from the substrate (302), to minimize adverse signal interaction between passive component (314) signals and the substrate (302).

Receiver and method therefor

Abstract: Embodiments of the present invention relate generally to receivers. One embodiment relates to a digital FM receiver having multiple sensors (e.g. antennas). In one embodiment, the digital receiver includes a baseband unit having a channel processing unit. In one embodiment, the channel processing unit is capable of calculating or estimating a phase difference between the incoming signals prior to combining them. One embodiment uses phase estimation method for diversity combining the signals while another embodiment utlizes a hybrid phase lock loop method. Also, some embodiments of the present invention provide for echo-cancelling after diversity combining. An alternate embodiment of the channel processing unit utilizes a space-time unit to diversity combine and provide echo cancelling for the incoming signals. Other embodiments of the present invention allow for the incoming signals from the multiple antennas to pass through the baseband unit uncombined, where the incoming signals may have different data formats.

Method and apparatus for operating a communication bus

Abstract: Embodiments of the present invention related generally to communication systems. One embodiment contemplates a method for operating a communication bus where the method includes detecting a start of frame symbol on the communication bus; determining a length of the start of frame symbol; detecting a start of a synchronization field on the communication bus; determining a length of an adjusted synchronization field; determining if the length of the adjusted synchronization field is less than the length of the start of frame symbol; and if the length of the adjusted synchronization field is less than the length of the start of frame symbol, concluding that the start of frame symbol is valid and concluding that the synchronization field is valid. Embodiments of the invention may be used, for example, with the Local Interconnect Network (LIN) protocol.

Cladding of a conductive interconnect for programming a MRAM device using multiple magnetic layers

Abstract: A cladded conductive interconnect for programming a magnetoresistive memory device which includes a conductive material with a length, a first barrier conductive material positioned on the conductive material, and a multi-layer cladding region positioned along the length of the conductive material wherein the multi-layer cladding region includes N ferromagnetic layers, where N is a whole number greater than or equal to two, and wherein the multi-layer cladding region further includes at least one spacer layer, wherein the spacer layer can include a metal, an insulator, or an exchange interaction material, and wherein the spacer layer is sandwiched therebetween each adjacent ferromagnetic layer.

Recording of result information in a built-in self-test circuit and method therefor

Abstract: An integrated circuit has a Built-In Self-Test (BIST) controller ( 10 ) that has a sequencer ( 16 ) that provides test algorithm information for multiple memories ( 44, 46, 48, 50 ). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces ( 32, 34, 36, 38 ) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. When test algorithms fail or complete execution, pertinent BIST information is stored in non-user addressable space of the multiple memories.

Design verification system for avoiding false failures and method therefor

Abstract: Embodiments of the present invention provide for a method and system for verifying that an implementation design is functionally equivalent to a predetermined functionality of a reference design where the reference and implementation designs may correspond to a portion of a larger integrated circuit design. The use of Symbolic Trajectory Evaluation (STE) to compare the designs may result in false failures. Therefore, one aspect of the present invention provides for comparing an expected result from the reference design to an actual result of the implementation design in order to determine a set of failure conditions. Constraints are then selectively applied to the set of failure conditions in an attempt to remove them. Another aspect of the present invention allows for the selective use of symbols rather than “X”s (unknowns) in order to avoid false failures due to certain inputs of the implementation design not being properly stimulated.