Showing papers by "STMicroelectronics published in 1993"

Cam with additional row cells connected to match line

Abstract: A method of accessing a content addressable memory having a plurality of RAM cells connected in an array of rows and columns, each row having a plurality of cells for storing a data word, at least one additional cell for storing a checking bit and a match line for providing a signal to indicate when a match occurs between an input data word and data stored in a row of cells, which method comprises storing in at least one row of cells a data word in data cells of the row and a checking bit in said at least one additonal cell of the row, the checking bit having a value dependent on the content of the data word in accordance with an error checking system, and controlling a memory accessing system to effect an associate operation by inputting to the columns of cells an input word with an input checking bit dependent on said input word in accordance with the same error checking system, comparing the input word and input checking bit with stored contents of each row of cells and in any row where a mismatch of the input data word with the stored data word occurs causing at least two cells in that row to change a signal level on a match line for that row, said memory accessing system being arranged to operate with a time delay for each associate operation which is less than that required for a single cell mismatch. The invention also provides a content addressable memory.

Voltage boosting circuit of the charge pump type with bootstrap oscillator

Abstract: The invention relates to charge-pump circuits used for the generation, in an integrated circuit, of an internal supply voltage Vpp which is considerably greater than the external supply voltage Vcc. In a charge pump configuration with capacitors and transistors, certain transistors must be driven by bootstrapped logic signals, i.e., having a logic level which is greater than Vcc in order to overcome the threshold voltage of the transistors. According to the invention, there is an oscillator followed by a phase splitter stage which is in turn followed by a bootstrap amplifier stage. The oscillator is a ring oscillator having a number of logic gates which is as small as possible, preferably only three. A satisfactory frequency stability of the charge pump is thus obtained and therefore its design is made easier and its adaptability to various electronic circuits is improved.

A CMOS low-distortion fully differential power amplifier with double nested Miller compensation

Abstract: A four-stage fully differential power amplifier using a double-nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and stability conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and total harmonic distortion (THD) is -83 dB for a -V/sub p-p/ differential output signal at 10 kHz and a load of 50 Omega . With an 8 Omega load and for a 10-kHz, 4-V/sub p-p/ output signal, THD is -68 dB. The chip area is 0.625 mm/sup 2/ in a 1.5- mu m single-poly, double-metal, n-well CMOS technology. >

VDMOS transistor with improved breakdown characteristics

Abstract: The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

Method and apparatus for operating polyphase DC motors using a PWM chopping signal in zero crossing determination

Abstract: A method and circuit for operating a polyphase dc motor having a plurality of driving coils is presented. In one of the available operating modes, drive current supplied to the driving coils is chopped, in PWM fashion to control the maximum current delivered thereto by turning the drive current on and off. Zero crossings of a back emf voltage of the driving coils that are connected into a floating state are detected for producing a commutation signal, and the detection of zero crossings is inhibited for a predetermined time after the drive current is turned off during the chopping step to avoid detecting a false zero crossing. In normal operation, detected back emf sampled voltages are forwarded to back emf detection circuitry responsive to a high frequency clock.

Fuse circuitry to control the propagation delay of an IC

Abstract: According to the present invention, integrated circuitry provides for the ability to selectively introduce delays into the timing of the integrated circuit, without the expense and time associated with methods used in the prior art. As a minimum, a fuse element having at least one fuse and a transistor element having at least one transistor are placed in parallel to each other between a voltage supply of a gate of the integrated circuit and a corresponding voltage supply of the integrated circuit. When the fuse element is intact, the fuse element provides a relatively low resistance path from the voltage supply of the gate and the corresponding voltage supply of the integrated circuit. However, upon blowing the fuse element, this low resistance path is no longer available. An increased resistance path through the transistor element must be used, and the integrated circuit is slowed down accordingly. The amount of delay introduced to the delay element is a function of the values of the transistors in the transistor element.

Enhanced planarization technique for an integrated circuit

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

An integrated hall•effect apparatus for detecting the position of a magnetic element

Abstract: For detecting the position of a magnetic element having a field component zeroing in at least one point in space, typically in a plane, a plurality of elementary Hall-effect sensors are integrated side by side and aligned in a direction perpendicular to the zeroing field component and to the current flowing through the elementary sensors. The elementary sensor generating a zero output voltage therefore indicates the zero position of the field component and consequently the position of the magnetic element with respect to the position sensor, so that The outputs of the elementary sensors provide a quantized numeric code indicating the position of the magnetic element.

Virtual ground read only memory circuit

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.

Column redundancy architecture for a read/write memory

Abstract: An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder, associated with each column. A plurality of redundant sense amplifiers are each associated with selected redundant columns. Each of the redundant column decoders includes a set of fuses for storing the column address responsive to which its associated redundant column is to be selected. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each redundant column decoder corresponding thereto, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.

Semiconductor contact via structure and method

Abstract: A contact opening through an insulating layer is filled with metal and etched back to form a metal plug within the opening. A metal interconnect line can then be formed over the contact, and makes electrical contact with the metal plug. Since the contact opening is filled by the metal plug, it is not necessary for the metal signal line to have a widened portion in order to ensure enclosure.

Circuit assembly having interposer lead frame.

Abstract: A circuit assembly includes a finger lead assembly (12) having structure for supporting an interposer substrate assembly (14) and an electronic circuit device (16), the substrate assembly having conductive elements for providing electrical connection between finger leads (18) of the lead assembly (12) and respective circuit sections within the circuit device. The circuit device (16) is mounted proximate to an upper surface of the substrate assembly (14). At least one decoupling capacitor (52a,52b) is mounted on a lower surface of the substrate assembly (14) at a level below that of the finger leads (18) and electrically connected, through circuitry within the substrate assembly (14) including inter-level via connectors (88,92b), to respective circuits within the circuit device (16).

A semiconductor memory with improved redundant sense amplifier control

Abstract: An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder associated with each column, each of which includes a set of address fuses into which an address is programmed, responsive to which its associated redundant column is to be selected. A plurality of redundant sense amplifiers are each associated with selected redundant columns, and are each controlled to begin the sense operation prior to propagation of the address signal through the redundant column decoders and summing circuitry. In the event that the received memory address does not match any of the programmed values in the redundant column decoders associated with a redundant sense amplifier, the sense operation is terminated. In this way, the sense operation is not delayed by the additional delay required for redundant decoding and propagation of the redundant address signals, and thus the access time penalty for accessing a redundant memory cell is much reduced or eliminated. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each associated redundant column decoder, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.

Structure and method for flash eprom memory erasable by sectors

Abstract: A device for the erasure of sectors of a flash EPROM memory map comprises routing means to apply an erasing voltage to several sectors selected simultaneously by a predetermined resistor for all the sectors. Advantageously, the routing means enable the application of the erasing voltage to a sector selected individually by a resistor proper to the sector.

Data flow control mechanism utilizing low level flow control codes

Abstract: A communications device, particularly but not exclusively for use with a routing circuit, transmits and receives message packets. An output buffer converts data and flow-control information into a plurality of bit sequences and transmits them at a predetermined frequency. An input buffer decodes informing sequences into data items and flow control information. The input buffer can store the data items and count them and transmit flow control information to the output buffer.

Integrated circuit with planarized shallow trench isolation

Abstract: A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface. According to an alternative embodiment, the formation of the sidewall spacers may be done in such a manner that narrower recesses remain filled with the material of the sidewall spacers.

Method and apparatus for providing the lock of a phase-locked loop system to a frequency sweep

Abstract: Synchronization of the output of an internally-driven VCO to an exterior clock signal is obtained by using the exterior clock signal to re-start the VCO at every exterior clock pulse, until the pre-set VCO frequency is reached. At that point, the re-starting of the VCO ceases, and the VCO locks onto the internal signal it is designed to track. One application of this circuit is for enabling a smooth transition between open-loop, ramp-up of a polyphase DC motor, enclosed-loop operation of the motor to closed loop operation. Implementation of the circuit described phase-synchronizes the output of a phase-switching PLL loop, which is tracking the back emf of the motor, to the external clock used for motor ramp-up, so that there is no "jolt" in the motor at the transition from open-loop to closed-loop operation of the motor.

Method for the testing of integrated circuit chips and corresponding integrated circuit device

Abstract: In a method for the testing of integrated circuits on wafers, the testing is facilitated by setting apart a test circuit zone on the wafer. The test circuit zone comprises contact pads to which it is possible to apply the tips of a tester, and also comprises a demultiplexer to transmit test stimuli to one out of N buses at the output of the demultiplexer. The output buses of the demultiplexer extend between the rows of chips on the wafer. Column selection conductors extend between the columns of chips. The demultiplexer and a decoder, both controlled directly by the tester, enable the selection of one chip at a time for testing. The testing tips are not shifted from one chip to the next one. The wafer is then sliced into individual chips.

Automatic synthesis, analysis and implementation of a fuzzy controller

Abstract: A method based on the cell-to-cell approach is proposed for extracting the control rules for a fuzzy controller. This procedure was implemented to control the position of a DC motor. To obtain high performance in terms of fuzzy inferences per second (FIPS) that complex control requires, the rules and the membership functions have been implemented via a hardware solution, WARP. WARP is a dedicated VLSI machine with an architecture designed to efficiently exploit data provided by the cell-to-cell approach. The global architecture along with some generalities on the particular approach are presented. >

A 3.3-V 800-nV/sub rms/ noise, gain-programmable CMOS microphone preamplifier design using yield modeling technique

Abstract: A 3.3-V CMOS low-noise gain-programmable microphone amplifier with a high-impedance balanced input is presented. The preamplifier allows gains from 20 to 35 dB to be set by software control in 1-dB steps with 0.05-dB accuracy. Typical measured V/sub OS/ is 0.8 mV, V/sub OS/ drift is 1 mu V/C, input-referred p-weighted noise is 0.8 mu V/sub rms/ and total harmonic distortion (THD) is -70 dB. The active area is about 350 mils/sup 2/, and power consumption is 1.7 mW at 3.3-V supply and 2.9 mW at 5-V supply. These results have been obtained through an intensive use of the yield modeling technique for yield-performance optimization during the design phase, and by applying a common-centroid cross-coupled strategy to the layout of all the ideally matched MOS transistors in the input stage. >

Cache tag memory

Abstract: A cache tag memory device having a memory array comprising a first single-port memory array, a second single-port memory array, and a dual-port memory array. A first port, accessed by a local processor, may read from and write to its corresponding single-port memory array and the dual-port memory array. A second port, accessed through a global system bus, may also read from and write to its corresponding second single-port memory array and the dual-port memory array Both ports operate asynchronously relative to each other. Status bits indicating the status of the entries in the first and second single-port memory arrays are stored in the dual-port memory array and may be altered by the global system while the local processor is performing its operations.

Control interface device for an electric motor

Abstract: A control interface device for an electric motor, particularly an electric motor for operating servomechanisms on a vehicle, which includes a conductor frame, an active integrated component mounted on the conductor frame, and a plurality of electric connectors A single insulating, one-piece enclosing body contains the conductor frame with the active integrated component and the electric connectors included to the conductor frame Thus, all of the elements required for powering and controlling the motor are gathered inside a single enclosing body which is convenient to handle and connect

Overtemperature warning cycle in operation of polyphase DC motors

Abstract: A method and integrated circuit for providing drive signals to a polyphase dc motor. The integrated circuit is fabricated on a semiconductor substrate for providing drive signals to a polyphase dc motor. The circuit includes a coil drive circuit for connection to drive coils of the motor to selectively supply drive currents thereto in a predetermined sequence. A sequencer circuit commutatively selects the drive coils to which the drive currents are selectively supplied, and a motor, speed controlling circuit controls the speed of the motor by controlling the speed of commutation. A temperature sensing element, such as a diode, is fabricated in the substrate to indicate the temperature of the substrate, and a temperature measuring circuit is connected to the temperature sensing element and to the motor speed controlling circuit to operate the motor speed controlling circuit to slow the speed of the motor when the temperature of the substrate exceeds a first predetermined temperature. If desired, temperature measuring circuit can include a circuit for measuring a second temperature higher than the first predetermined temperature to operate a shut down circuit to turn off the motor if the substrate temperature is too high.

Compensating delay element for clock generation in a memory device

Abstract: Circuits and methods for generating a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device is disclosed. In a first embodiment, a delay circuit is provided for generating an output clock signal for controlling a circuit internal to an integrated circuit, such as a clocked sense amplifier in a memory device, relative to an earlier timing signal, such as a row select signal. The delay circuit is implemented by components having their design parameters, such as transistor dimensions and transistor orientation, corresponding to elements in an active portion of the circuit, such as memory cell transistors. Process variations that affect the electrical properties and the speed of the transistors in the active portion of the circuit will similarly affect the electrical properties and speed of transistors in the delay circuit, so the delay circuit can track and automatically compensate for process-induced speed variations, eliminating the need for large design time margins. Alternative embodiments are also disclosed which account for the threshold voltage drops across pass transistors in a memory array, and mimic the memory cell read current, when generating a sense amplifier clock signal.

Variable gain amplifier for low supply voltage systems

Abstract: A variable gain amplifier which includes a first voltage-to-current amplifier having a fixed gain; a second voltage-to-current amplifier having a variable gain, functioning in parallel to said first amplifier; a gain control and stabilization variable current generator; and a current-to-voltage converter. Current output signals produced by said first and second amplifiers and by said variable current generator are summed and the resulting current signal is converted to a voltage signal by said converter.

Self-aligned method for forming contact with zero offset to gate

Abstract: A method for self-aligned zero-margin contacts to active and poly-1, using silicon nitride or other dielectric material with low reflectivity and etch selectivity to oxide for an etch stop layer and also for sidewall spacers on the gate.

Cache memory system including a RAM for storing data and CAM cell arrays for storing virtual and physical addresses

Abstract: A fully associative cache memory for virtual addressing comprises a data RAM (50), a first CAM cell array (51) for holding virtual page addresses which each require address translation to identify a physical page in a main memory, a second CAM cell array (52) holding line or word in page addresses which remain the same for virtual and physical addresses, a physical address memory (53) for holding physical page addresses for the main memory corresponding to virtual page addresses in said first array (51), said first array (51) being connected both to said physical address memory (52) to access said physical address memory in response to a hit output from said first CAM cell array and to control circuitry (57) coupled between said first and second arrays (51,52) and the data RAM (50) to access the data RAM (50) in response to hit outputs from both said first and second CAM cell arrays (51,52).

PTAT current source

Abstract: A current source for producing a current that is proportional to absolute temperature (i.e., "PTAT") is disclosed. The current source is based upon a circuit having a pair of current mirrors, one based upon MOS transistors and the other based upon bipolar transistors, where each of two legs in the current source include the series connection of one of the MOS transistors with one of the bipolar transistors. Further included in the disclosed circuit is a series connection of three MOS startup transistors, useful in starting up the current source in a non-critical manner. A startup current source, sourcing a non-critical startup current, turns on one of the MOS startup transistors that is connected in current mirror fashion with the MOS transistor current mirror, turning on both current mirrors. As the output current increases, the current through the MOS startup transistors also increases, until equilibrium is achieved. Early effects in the bipolar transistor current mirror are eliminated by maintaining the gate-to-source voltage of the MOS transistors equal, without requiring cascode transistors, and thus maintaining low voltage operating capability.

IC controlled DC motor

Abstract: A DC motor having a housing (2), a hub member (8) rotatably supported by the housing, a flexible printed circuit board (40) fixedly mounted on the housing, and an IC chip (48) mounted on the flexible printed circuit board and located facing a recess (32) formed in the housing. The hub member has a shaft (24) rotatably supported by a bearing (4,6) within the recess. The flexible printed circuit board has a metal layer (50) for mounting the IC chip, the metal layer being isolated from a wiring pattern (44) formed on the printed circuit board. The wiring pattern on the flexible printed circuit board is directly connected to a connection pin (36) connected to the motor wiring (20).

Method for forming an aluminum contact through an insulating layer

Abstract: A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.