Showing papers in "Journal of Computer Science and Technology in 1986"
TL;DR: Two varieties of the public key cryptosystem in [1] are given which can also be used to implement digital signatures and are given in this paper.
Abstract: This paper gives two varieties of the public key cryptosystem in [1] which can also be used to implement digital signatures.
41 citations
Journal Article•
TL;DR: In this article, the authors consider rewrite rules with conditions, such as they arise, e.g., from algebraic specifications with positive conditional equations, and prove confluence results and termination results for some well-known reduction strategies.
Abstract: Algebraic specifications of abstract data types can often be viewed as systems of rewrite rules. Here we consider rewrite rules with conditions, such as they arise, e.g., from algebraic specifications with positive conditional equations. The conditional term rewriting systems thus obtained which we will study, are based upon the well-known class of left-linear, nonambiguous TRSs. A large part of the theory for such TRSs can be generalized to the conditional case. Our approach is non-hierarchical: the conditions are to be evaluated in the same rewriting system. We prove confluence results and termination results for some well-known reduction strategies.
18 citations
[...]
TL;DR: This paper describes briefly the first large-scale vector computer system designed and produced in China—vector computer 757.
Abstract: This paper describes briefly the first large-scale vector computer system designed and produced in China—vector computer 757. The design philosophy, architecture, hardware implementation, software and performance of this computer are presented.
18 citations
TL;DR: It is proved that the 0/1 multi-knapsack optimization problem is NP-equivalent by using Turing reduction, and the corresponding decision problem isNP-complete in the strong sense.
Abstract: In this paper complexity of the 0/1 multi-knapsack problem is discussed. First we prove that the corresponding decision problem is NP-complete in the strong sense. For any fixed numberk of knapsacks, the problem is only NP-complete in the ordinary sense, but not NP-complete in the strong sense. Then, we prove that the 0/1 multi-knapsack optimization problem is NP-equivalent by using Turing reduction.
17 citations
TL;DR: In this paper, a method for weakly invertible finite automata with delay τ can be found, where τ is the delay of the inverses of the automata.
Abstract: In this paper, we first give a method by which, for any weakly invertible finite automatonM with delay τ, the set of all weak inverse finite automata ofM with delay τ can be constructed. We then give a method by which, for any invertible one, all its inverses with delay τ can also be constructed.
9 citations
TL;DR: All weakly invertible finite automata with delay τ of which M′ is a weak inverse with delay, can be constructed; and a universal nondeterministic finite automaton, for all infinite automata, is constructed.
Abstract: In this paper, we first give a method that for any inverse finite automaton M′ with delay τ, all inver tible finite automata with delay τ, of whichM′ is an inverse with delay τ, can be constructed; and a universal nondeterministic finite automaton, for all finite automata of whichM′ is an inverse with delay τ, can also be constructed. We then give a method that for any weak inverse finite automatonM′ with delay τ, all weakly invertible finite automata with delay τ of whichM′ is a weak inverse with delay, can be constructed; and a universal nondeterministic finite automaton, for all finite automata of whichM′ is a weak inverse with delay τ, can also be constructed.
6 citations
TL;DR: The inherent parallelism limits on several applications for vector computers, the parallel capabilities of several architectures and two ways (traditional instruction control flow and data control flow) by which the capabilities can be used are discussed.
Abstract: This paper discusses the inherent parallelism limits on several applications for vector computers, the parallel capabilities of several architectures and two ways (traditional instruction control flow and data control flow) by which the capabilities can be used. Then a scheme for a pipelined vector processor of multi-processing units is presented. The basic system structure and its function on highly sparse vector processing are described. A vector cache system and a distributed main memory are also considered, which are intended to sustain extremely high access rates for the processor. A microprocessor based vector processor is constructed, which can simulate the high performance version of the processor.
3 citations
TL;DR: It is shown that onlyO(j) of backtrack consumption is needed in IPODEM compared withO(2j) in PODEM on certain occasions, and that the former has higher test coverage than the latter.
Abstract: In this paper, an analysis of backtrack behavior in PODEM (the test generation algorithm for combinational circuits presented by P. Goel) is given. It is pointed out that there are still many unnecessary backtracks in PODEM on some occasions. A new test generation algorithm named IPODEM is therefore proposed in this paper. IPODEM is an improvement over PODEM with emphasis on backtrack of decision tree. A new backtrack approach is developed in this algorithm. It is shown that onlyO(j) of backtrack consumption is needed in IPODEM compared withO(2j) in PODEM on certain occasions. Experiments pointed out that these occasions appear in not small proportion. Several other techniques are applied in IPODEM to accelerate test generation process in other aspects. Experimental results demonstrated that IPODEM is faster than PODEM for both hard-testing and easy-testing single stuck fault, and that the former has higher test coverage than the latter.
2 citations
TL;DR: A new clustering algorithm ISOETRP has been developed that is suitable to hierarchical pattern classification and the overall objective to be optimized is GAIN=Entropy Reduction/(Overlap+1).
Abstract: A new clustering algorithm ISOETRP has been developed. Several new objectives have been introduced to make ISOETRP particularly suitable to hierarchical pattern classification. These objectives are: a) minimizing overlap between pattern class groups, b) maximizing entropy reduction, and c) keeping balance between these groups. The overall objective to be optimized is GAIN=Entropy Reduction/(Overlap+1).
2 citations
TL;DR: This paper presents a recovery technique for distributed communicating process systems that handles both hardware faults and software faults uniformly and brings an extremely small amount of execution overhead to nonfailing processes and can be implemented easily.
Abstract: This paper presents a recovery technique for distributed communicating process systems. It handles both hardware faults and software faults uniformly. Differing from other recovery techniques, it brings an extremely small amount of execution overhead to nonfailing processes and can be implemented easily. It can be applied to a programming procedure to mask the software design errors or imbeded into an operating system to enhance the reliability of the whole system. The theoretical work is carried out first, then the implementation problems are considered and the evaluation techniques are discussed last.
2 citations
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TL;DR: This paper presents a kernel language KLND on the basis of analysing the kernel language requirements of new generation computer systems, which have the ability of know-ledge processing, the parallelism, the elegant mathematical properties of the computation model, and the suitability for writing large scale softwares.
Abstract: This paper presents a kernel language KLND on the basis of analysing the kernel language requirements of new generation computer systems. These requirements are: the ability of know-ledge processing, the parallelism, the elegant mathematical properties of the computation model which is appropriate for working as the basis of the novel architecture design, and the suitability for writing large scale softwares.
TL;DR: An overview of a distributed programming language called DMODULA, which is intended for the programming in a distributed environment, which develops module concepts of its ancestor, MODULA-2, and provides features of generic and remote procedure calls.
Abstract: This paper presents an overview of a distributed programming language called DMODULA, which is intended for the programming in a distributed environment. DMODULA develops module concepts of its ancestor, MODULA-2, and provides features of generic and remote procedure calls. DMODULA has been implemented on the ZOZ system, a distributed microcomputer system consisting of several LSI-11 microcomputers, which was designed and implemented at Nanjing University in 1982.
TL;DR: The representation of regular strokes and irregular strokes of Chinese characters and the method for transforming the compressed representation into dot matrix are described and the result is satisfactory, and the cost performance ratio of the typesetting system is significantly improved by the technique.
Abstract: Font storage requirement is a crucial problem in developing Chinese typesetting system. A unique data compression technique is adopted in the system. The representation of regular strokes and irregular strokes of Chinese characters and the method for transforming the compressed representation into dot matrix are described in the paper. The result is satisfactory, and the cost performance ratio of the typesetting system is significantly improved by the technique.
TL;DR: Using the concept of multiple signatures, the error detection capability of siguature analyzer can be enhanced by changing the connection between signature analyzer and circuit-under-test, or changing the characteristic polynomialp(x) of signature Analyzer.
Abstract: A new generalized parallel signature analyzer with external Exclusive-OR gates (GPSA-EE) is presented. It allows the signature analyzer to have twice the number of inputs compared with an original parallel signature analyzer. The equivalence between a GPSA-EE and an SSA-EE (serial signature analyzer) is established. Using the concept of multiple signatures, the error detection capability of siguature analyzer can be enhanced by changing the connection between signature analyzer and circuit-under-test, or changing the characteristic polynomialp(x) of signature analyzer.
TL;DR: The SEG system is outlined and the design principles and implementation techniques of the system are discussed, which ensure that any program edited by SEG is syntactically correct.
Abstract: SEG is a syntax-directed editor generator consisting of three parts: Meta, a meta language which describes BNF-like syntax; a parser, which parses the syntax descriptions written in Meta and generates their driver tables; a syntax-directed editor, which performs editing operations using a table. Similar to its ancestors (e.g. CPS, Gandalf), SEG is characterized by the following features: i) it is for a variety of languages so that the editor of a specific language can be easily produced; ii) multifile can be edited in multiwindow; iii) private environments can be set up by users; iv) the PC-mouse with the dedicated menus enables users to enter commands correctly and quickly; v) pretty-printing of program documents is done automatically or manually. Like other syntax-directed editors, any program edited by SEG is syntactically correct. This paper outlines the SEG system and discusses the design principles and implementation techniques of the system.
TL;DR: A general review of Chinese character processing systems developed in China is presented and it is pointed out that computer-aided component keying-in scheme is more ergonomical and promising in the near future.
Abstract: A general review of Chinese character processing systems developed in China is presented. Three main categories of existing entry schemes, i.e. character entry, encoding and component keying-in, are described. After examing the diversified encoding schemes based on phonetics, shape and phonetics-shape, it is pointed out that computer-aided component keying-in scheme is more ergonomical and promising in the near future. Section of Main Features gives an overall picture of the Chinese editor, character font, software for bilingual processing, display and printer for Chinese characters. Then the standardization of the character font, code for information exchange, machine code as well as Chinese character terminal are discussed. Finally, an overview of the applications of Chinese character processing systems in the enterprises, offices, facilities for public service and Chinese medical diagnosis are given.
TL;DR: A speaker-dependent isolated word recognizer which is dedicated for Chinese character input is introduced which offers an effective solution to the large-vocabulary recognition problem by carrying out recognition hierachically.
Abstract: In this paper, we introduce a speaker-dependent isolated word recognizer which is dedicated for Chinese character input. The method presented here offers an effective solution to the large-vocabulary recognition problem by carrying out recognition hierachically. The vocabulary consists of 800 to 1000 words. The average recognition rate is 90% when monosyllable words takes up one third of the vocabulary. Recognition rate can reach 95% by selecting from the top 20 candidates.
TL;DR: This paper gives the method to solve large cycling cover tables of these problems with cover-matrix complementation (sharp operation) and can give the optimal solutions and need not store the covering matrix.
Abstract: This paper describes the partitioning of the set of the Boolean equations generated by the hardware logic translator and the conversion of the subsets into cube arrays. Subsequent to this, it is aimed: (1) to find out the minimal sets of input variables; (2) to finish the logic minimization; and (3) to decompose a large logic array into smaller ones to meet the design constraints if necessary.
TL;DR: This paper proposes synchronous operations for dataflow computations and their model, and the outline of the implementation, S DS, of the model and its functional programming language, SDSFP, are described.
Abstract: Asynchronous operations in dataflow computers bring about some problems. In this paper, synchronous operations for dataflow computations and their model are proposed, and the outline of the implementation, SDS, of the model and its functional programming language, SDSFP, are described. The architecture of the first version of SDS (SDS-1) is discussed in detail.
TL;DR: This paper presents an LFSR design with non-maximum length to serve as a BITPG to generate a given test setT, which efficiently saves testing time.
Abstract: Built-in testing is currently of more concern due to the difficulties in testing a VLSI by using an external tester. In addition, Built-In Testing is also necessary for on-line testing and a fault-tolerant computing system. Using a Linear Feedback Shift Register (LFSR) as a built-in test pattern generator (BITPG) is a realistic and simple approach. An LFSR with maximum length can generate pseudo-random test patterns or all non-null vectors for exhaustive testing. This paper presents an LFSR design with non-maximum length to serve as a BITPG to generate a given test setT, which efficiently saves testing time. A search-verification process for designing this kind of LFSR is employed and implemented by the program SVBITPG. This paper presents the diagram of the program and gives some examples to illustrate the design of the BITPG.
TL;DR: The architecture of the graphics system is characterised by the distribution on the machines in the network of graphics facilities provided by several graphics subsystems with various capabilities but compatible functionality, and the distributed processing of graphics across the network.
Abstract: Design of a general purpose graphics system in a computer network environment requires that the architectural design of the graphics system be suited to such an environment and the advantages of the network environment be taken for distributed graphics processing and the sharing of resources. An architectural model is designed to meet these requirements. The model is characterised by the distribution on the machines in the network of graphics facilities provided by several graphics subsystems with various capabilities but compatible functionality, and the distributed processing of graphics across the network. This design structure has been shown to be viable by using it as the basis for the implementation of the graphics system for the MU6G network at University of Manchester. The design methodology and the structure of the graphics system are described in the paper.
TL;DR: An improved algorithm based on the next node routing principle, in which the candidate shortest distance to the destination node is the entry, is proposed in this paper and proved by the analysis and simulation.
Abstract: An improved algorithm based on the next node routing principle is proposed in this paper. In this algorithm there is a column added to the classical routing table, in which the candidate shortest distance to the destination node is the entry. When a link fails, the new shortest path in the nodes connected directly with the failure link can be found immediately (it is just the candidate shortest path before failure). For all other nodes in which routing tables should be changed, the required number of control messages and time for convergence are also less than Tajibnapis‖ algorithm and Predecessor algorithm. The message looping problem does not exist in duplex loop networks and is radically improved in mesh networks. These statements are proved by the analysis and simulation in this paper. From the simulation results of a 30-node mesh network, when one link goes down, the total number of control messages generated during convergence with this algorithm on the average is about 30% of Tajibnapis‖ algorithm. The iterations required is 50% of Tajibnapis‖ algorithm. The memory space required and computation complexity in nodes are almost the same as the two algorithms mentioned above and the algorithm implementation is as easy as well.
TL;DR: Experimental result given in this paper indicates that these Almost Optimal Dynamical 2–3 trees have very good performance at node-visit cost.
Abstract: This paper presents a principle to create Almost Optimal Dynamical 2–3 trees based on the theory of Milleret al.,[4] and gives a searching algorithm, an insertion algorithm and a deletion algorithm for these 2–3 trees. Experimental result given in this paper indicates that these 2–3 trees have very good performance at node-visit cost. We discuss asymptotic property of the 2–3 trees asN→∞, and evaluate its approximate height,h=log2.45(N+1), whereN is the number of nodes of a 2–3 tree. Finally, this paper analyses the time complexities of the algorithms, which areO(log2.45(N+1)).
TL;DR: An efficient method for simplifying a multivalued SULM network that can realize M can be constructed by cascading M/π andM′ by employing a cascade decomposition on aMultivalued sequential machineM.
Abstract: An efficient method for simplifying a multivalued SULM network is presented in this paper. This method employs a cascade decomposition on a multivalued sequential machineM. At first we decomposeM into two simpler machinesM/π andM′. Instead of the traditional normal tree type network, a simpler SULM network that can realizeM can be constructed by cascadingM/π andM′.
TL;DR: The Chinese information processing system (CIPS) introduced in this paper can produce graphs, tables, flowcharts, mathematical equations, forms and also provides typesetting facilities.
Abstract: The Chinese information processing system (CIPS) introduced in this paper can produce graphs, tables, flowcharts, mathematical equations, forms and also provides typesetting facilities. The system can process not only Chinese text but also English text or a mixture of them. It is written in C language and runs on VAX II/780 under Unix operating system. The CIPS system is very easy to use and provides user-defined macro which allows abbreviations of commonly used Chinese phrases and reduce the complexity of Chinese characters coding.
TL;DR: This is an introduction for Escher—the geometrical layout system, which is a hierarchical structure composed of cells, wires, connectors between wires, and pins that connect wires to cells.
Abstract: This is an introduction for Escher—the geometrical layout system. An Escher circuit description is a hierarchical structure composed of cells, wires, connectors between wires, and pins that connect wires to cells. Cells may correspond to primitive circuit elements, or they may be defined in terms of lower level subcells. Unlike other geometrical layout systems, a subcell may be instance of the cell being defined. When such a recursive cell definition is instantiated, the recursion is unwound in a manner reminiscent of the procedure call copy rule in Algol-like programming languages. Cell specifications may have parameters that are used to control the unwinding of recursive cells and to provide for cell families with varying numbers of pins and other internal components. With examples we illustrate how the Escher system might be used. We also briefly describe some basic rules for moving circuit components around in obtaining a layout.
TL;DR: AGDL, whose rules are easy to read, is an applicative language with abstract data types, and it will be used as an important tool language to develop compiler generators by NCI.
Abstract: AGDL is a definition language for attribute grammars. It is a specification language used to generate a compiler automatically. AGDL, whose rules are easy to read, is an applicative language with abstract data types, and it will be used as an important tool language to develop compiler generators by NCI.
TL;DR: A new parallel logic programming language—HPARLOG developed by us is described, and a new scheme for the AND-parallelism implementation in logic Programming language is proposed, which resolves the instantiation conflict on sharing-variables and decreases the dynamic complexity of the programs.
Abstract: In this paper, a new parallel logic programming language—HPARLOG developed by us is described, and a new scheme for the AND-parallelism implementation in logic programming language is proposed. This scheme not only resolves the instantiation conflict on sharing-variables, thoroughly explores the parallelism of the programs with incrementally constructed data structure, but also decreases the dynamic complexity of the programs. In addition, a pseudo-copy based memory management scheme to enhance the locality of goal processes and lower the overhead of program execution is proposed.
TL;DR: A method of computing Boolean difference by means of transition operators that considerably simplifies the computational complexity and introduces a method in which partial test patterns along a given path can be generated.
Abstract: In this paper we have proposed a method of computing Boolean difference by means of transition operators. This method considerably simplifies the computational complexity. Particularly, when the method is used in the test generation of digital circuits, the Boolean difference can be calculated iteratively from the outputs of gates to their inputs level by level, no matter whether there are reconvergent fanout lines or not. When there are m different paths from a given fault line to the primary output of the circuit, using traditional Boolean difference methods, the result formula will contain 2m−1 product terms, whereas using the method presented in this paper, the result formula will contain onlym product terms. On the other hand, the m product terms are connected by “OR” operators, therefore it is very convenient to generate partial test patterns. We also introduce a method in which partial test patterns along a given path can be generated. The method discussed in this paper have been used in the test generation of the PCBs of several computers and the results were quite satisfactory.